diff options
| author | Vitaly Andrianov <vitalya@ti.com> | 2014-07-25 22:23:19 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-25 10:48:12 -0400 |
| commit | 61f66fd5a81b97478e9d14326c1059baa6626680 (patch) | |
| tree | 9739805fd9589de9edc6fb253d333b785f6d3421 /arch/arm/cpu/armv7/keystone/clock-k2e.c | |
| parent | 9352697aa060e9b1b5d891e4490fdfa6f5ba6114 (diff) | |
| download | u-boot-61f66fd5a81b97478e9d14326c1059baa6626680.tar.gz | |
keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/keystone/clock-k2e.c')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/clock-k2e.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c index 42092e1060..31f66613ef 100644 --- a/arch/arm/cpu/armv7/keystone/clock-k2e.c +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c @@ -17,6 +17,22 @@ const struct keystone_pll_regs keystone_pll_regs[] = { [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, }; +int dev_speeds[] = { + SPD800, + SPD850, + SPD1000, + SPD1250, + SPD1350, + SPD1400, + SPD1500, + SPD1400, + SPD1350, + SPD1250, + SPD1000, + SPD850, + SPD800 +}; + /** * pll_freq_get - get pll frequency * Fout = Fref * NF(mult) / NR(prediv) / OD |