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authorMario Six <mario.six@gdsys.cc>2018-08-06 10:23:46 +0200
committerSimon Glass <sjg@chromium.org>2018-09-18 08:12:21 -0600
commitd2166319df17286b2a3e2a1a7ce89f01e4f8bac9 (patch)
treeb102f2c59d51a124be29bf9f4e6a0bae60e6fdab /Documentation
parent19fbdca47b3d847824ada3ab2ed575019c88516e (diff)
downloadu-boot-d2166319df17286b2a3e2a1a7ce89f01e4f8bac9.tar.gz
misc: Add MPC83xx serdes driver
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt24
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+MPC83xx SerDes controller devices
+
+MPC83xx SoCs contain a built-in SerDes controller that determines which
+protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
+and how the lines are configured.
+
+Required properties:
+- compatible: must be "fsl,mpc83xx-serdes"
+- reg: must point to the serdes controller's register map
+- proto: selects for which protocol the serdes lines are configured. One of
+ "sata", "pex", "pex-x2", "sgmii"
+- serdes-clk: determines the frequency the serdes lines are configured for. One
+ of 100, 125, 150.
+- vdd: determines whether 1.0V core VDD is used or not
+
+Example:
+
+SERDES: serdes@e3000 {
+ reg = <0xe3000 0x200>;
+ compatible = "fsl,mpc83xx-serdes";
+ proto = "pex";
+ serdes-clk = <100>;
+ vdd;
+};