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author | Tom Rini <trini@konsulko.com> | 2018-08-11 19:48:13 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2018-08-11 19:48:13 -0400 |
commit | 282ce6454c45409805e2c470bbec170d21a4bd35 (patch) | |
tree | b10634fb8f5d0e8ef3b772d6059f66138d8bbc5a /Documentation | |
parent | a032e0a6aed208977f48e78d2cc497b91543beaf (diff) | |
parent | 25a9f9747a84b36f61f575d592eddc96bce5dabb (diff) | |
download | u-boot-282ce6454c45409805e2c470bbec170d21a4bd35.tar.gz |
Merge branch 'master' of git://git.denx.de/u-boot-video
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt b/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt new file mode 100644 index 0000000000..110788fa91 --- /dev/null +++ b/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt @@ -0,0 +1,22 @@ +gdsys AXI busses of IHS FPGA devices + +Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which +the connected devices (usually IP cores) can be controlled via software. + +Required properties: +- compatible: must be "gdsys,ihs_axi" +- reg: describes the address and length of the AXI bus's register map (within + the FPGA's register space) + +Example: + +fpga0_axi_video0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x170 0x10>; + + axi_dev_1 { + ... + }; +}; |