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authorLokesh Vutla <lokeshvutla@ti.com>2018-05-03 20:34:49 +0530
committerTom Rini <trini@konsulko.com>2018-05-06 13:35:40 -0400
commit7ce85318cfff5fd82a059131761559cba7fef309 (patch)
tree54a9427928027a68a0412c69619ed3b5a4c6fc52
parent535adee8692f89df3472f92ae68d6aa0efb883d7 (diff)
downloadu-boot-7ce85318cfff5fd82a059131761559cba7fef309.tar.gz
arm: mach-omap2: cache: Explicitly enable I cache
omap-common cache enabling sequence relies on cpu_init_cp15() (inside start.S) for enabling I-caches. But cpu_init_cp15() can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So enable I-caches if not enabled already. Debugged-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Tested-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
-rw-r--r--arch/arm/mach-omap2/omap-cache.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
index b37163a4f3..975ee1b020 100644
--- a/arch/arm/mach-omap2/omap-cache.c
+++ b/arch/arm/mach-omap2/omap-cache.c
@@ -44,7 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
void enable_caches(void)
{
- /* Enable D-cache. I-cache is already enabled in start.S */
+
+ /* Enable I cache if not enabled */
+ if (!icache_status())
+ icache_enable();
+
dcache_enable();
}