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| author | Stefan Roese <sr@denx.de> | 2020-05-14 11:59:06 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-07-18 14:23:25 +0200 |
| commit | a02bc1f99275a17e1d29886c8c69398e9313842d (patch) | |
| tree | 96ea7d1679416a235d2412e7123b2dc50eb0dc7e | |
| parent | a414281da4ce0761e898309fee4c489d43b4abb6 (diff) | |
| download | u-boot-a02bc1f99275a17e1d29886c8c69398e9313842d.tar.gz | |
mips: traps: Set WG bit in EBase register on Octeon
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 1 | ||||
| -rw-r--r-- | arch/mips/lib/traps.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7538e6b2e0..17381301ec 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -366,6 +366,7 @@ * Bits in the coprocessor 0 EBase register. */ #define EBASE_CPUNUM 0x3ff +#define EBASE_WG (_ULCAST_(1) << 11) /* * Bits in the coprocessor 0 config register. diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index b1ae02fcab..6ff9d20bd6 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr) saved_ebase = read_c0_ebase() & 0xfffff000; + /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= EBASE_WG; + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier(); |