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| author | Zong Li <zong.li@sifive.com> | 2021-09-01 15:01:40 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-09-07 10:34:29 +0800 |
| commit | 4d4222d07432faffe3a0fe35c483e116a28eb217 (patch) | |
| tree | d231a09a9223c329f6b3dde902a43695e2c96e26 | |
| parent | 43a21839285c1ba3b65534def898a2b5e2d46314 (diff) | |
| download | u-boot-4d4222d07432faffe3a0fe35c483e116a28eb217.tar.gz | |
common: board_r: support enable_caches for RISC-V
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
| -rw-r--r-- | arch/riscv/lib/cache.c | 4 | ||||
| -rw-r--r-- | common/board_r.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..686e699efb 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,7 @@ __weak int dcache_status(void) { return 0; } + +__weak void enable_caches(void) +{ +} diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c2451a2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -114,7 +114,7 @@ static int initr_reloc(void) return 0; } -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) /* * Some of these functions are needed purely because the functions they * call return void. If we change them to return 0, these stubs can go away. @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = { initr_trace, initr_reloc, /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) initr_caches, /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, |