diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2020-01-29 14:08:29 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2020-02-12 20:47:14 +0300 |
| commit | b8f3ce013700893a3ed4ae280a2aec0ab95af3de (patch) | |
| tree | 05dcaba57ebbcd01e6be16663a58919ad94e752f | |
| parent | 95f7103f943bff243df46592eca5dcb8957ab0ba (diff) | |
| download | u-boot-b8f3ce013700893a3ed4ae280a2aec0ab95af3de.tar.gz | |
CLK: HSDK: Check for PLL bypass firstly
Pll bypass has priority over enable/disable.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| -rw-r--r-- | drivers/clk/clk-hsdk-cgu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 56ef08c032..69e6b24b66 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -377,14 +377,14 @@ static ulong pll_get(struct clk *sclk) pr_debug("current configurarion: %#x\n", val); - /* Check if PLL is disabled */ - if (val & CGU_PLL_CTRL_PD) - return 0; - /* Check if PLL is bypassed */ if (val & CGU_PLL_CTRL_BYPASS) return PARENT_RATE; + /* Check if PLL is disabled */ + if (val & CGU_PLL_CTRL_PD) + return 0; + /* input divider = reg.idiv + 1 */ idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); /* fb divider = 2*(reg.fbdiv + 1) */ |