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| author | Sean Anderson <seanga2@gmail.com> | 2020-09-21 07:51:36 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-09-30 08:54:52 +0800 |
| commit | d4990a46485f2f6592ae29f2b822043dbdeae15d (patch) | |
| tree | cd415656cc2c7d527feae832c5026e4a23052ac4 | |
| parent | c41045411bbb64eeda2d404b79723f8d2802351c (diff) | |
| download | u-boot-d4990a46485f2f6592ae29f2b822043dbdeae15d.tar.gz | |
riscv: Match memory barriers between send_ipi_many and handle_ipi
Without a matching barrier on the write side, the barrier in handle_ipi
does nothing. It was entirely possible for the boot hart to write to addr,
arg0, and arg1 *after* sending the IPI, because there was no barrier on the
sending side.
Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/lib/smp.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..ab6d8bd7fa 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + __smp_mb(); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg); |