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| author | Heiko Stuebner <heiko.stuebner@theobroma-systems.com> | 2019-09-25 20:21:21 +0200 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-17 17:23:18 +0800 |
| commit | e61350a5f5f711fc4427bb1303c54d853db941e0 (patch) | |
| tree | f77e3bde0f5a5192337f1740cea2b445fc95357e | |
| parent | a907dc3f25fa90becb4202c7cf973b4fc5abaa1b (diff) | |
| download | u-boot-e61350a5f5f711fc4427bb1303c54d853db941e0.tar.gz | |
rockchip: misc: read cpuid either from efuse or otp
Newer Rockchip socs use a different ip block to handle one-time-
programmable memory, so depending on what got enabled get the cpuid
from either source.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/mach-rockchip/misc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index c0e4fdbc00..bed4317f7e 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -57,13 +57,18 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, const u32 cpuid_length, u8 *cpuid) { -#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) || CONFIG_IS_ENABLED(ROCKCHIP_OTP) struct udevice *dev; int ret; /* retrieve the device */ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(rockchip_efuse), &dev); +#elif CONFIG_IS_ENABLED(ROCKCHIP_OTP) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_otp), &dev); +#endif if (ret) { debug("%s: could not find efuse device\n", __func__); return -1; |