dm: test: clk: add the test for the ccf gated clock

Unlike the other clock types, in the case of the gated clock, a new
driver has been developed which does not use the registering routine
provided by the common clock framework.
The addition of the ecspi0 clock to sandbox therefore allows testing
the ccf gate clock.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>

3 files changed, 20 insertions, 0 deletions

diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
index 0619d04f0e..e90b860257 100644
--- a/drivers/clk/clk_sandbox_ccf.c
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -250,6 +250,10 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
 	clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 	       sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 
+	reg = 0;
+	clk_dm(SANDBOX_CLK_ECSPI0,
+	       sandbox_clk_gate("ecspi0", "ecspi_root", &reg, 0, 0));
+
 	clk_dm(SANDBOX_CLK_ECSPI1,
 	       sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 
diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h
index 296cddfbb0..c2616c27a4 100644
--- a/include/sandbox-clk.h
+++ b/include/sandbox-clk.h
@@ -50,6 +50,14 @@ static inline struct clk *sandbox_clk_divider(const char *name,
 			reg, shift, width, 0);
 }
 
+static inline struct clk *sandbox_clk_gate(const char *name, const char *parent,
+					   void __iomem *reg, u8 bit_idx,
+					   u8 clk_gate_flags)
+{
+	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
+				 reg, bit_idx, clk_gate_flags, NULL);
+}
+
 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 				       const char *parent_name,
 				       unsigned long flags,
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index 050fa80453..960cb2db0d 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -39,6 +39,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
 	rate = clk_get_parent_rate(clk);
 	ut_asserteq(rate, 20000000);
 
+	/* test the gate of CCF */
+	ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
+	ut_assertok(ret);
+	ut_asserteq_str("ecspi0", clk->dev->name);
+
+	rate = clk_get_parent_rate(clk);
+	ut_asserteq(rate, 20000000);
+
 	/* Test the mux of CCF */
 	ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
 	ut_assertok(ret);