diff options
| author | David Wu <david.wu@rock-chips.com> | 2019-11-26 09:39:50 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-12-06 00:06:23 +0800 |
| commit | 982fab393d1e0a866df1daeb2a0f692788a3814d (patch) | |
| tree | 113279bb442314652cfffae17cfb9185fad39603 | |
| parent | 0ed8f1e5f4c4acf0ca9ec158c503cd1cc5e9dfec (diff) | |
| download | u-boot-982fab393d1e0a866df1daeb2a0f692788a3814d.tar.gz | |
arm: dts: Add mac node for rk3308 at dtsi level
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/dts/rk3308.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi index 0eeec165d4..a5c0b72ae0 100644 --- a/arch/arm/dts/rk3308.dtsi +++ b/arch/arm/dts/rk3308.dtsi @@ -627,6 +627,28 @@ status = "disabled"; }; + mac: ethernet@ff4e0000 { + compatible = "rockchip,rk3308-mac"; + reg = <0x0 0xff4e0000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, + <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC>, <&cru ACLK_MAC>, + <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac", "clk_mac_speed"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; + resets = <&cru SRST_MAC_A>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; |