diff options
| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-07-12 20:03:09 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-08-15 08:50:02 +0200 |
| commit | a89441a74f6df1f75b942f6906724620fad2e8e1 (patch) | |
| tree | ec5c58398b5ca0f6b6b58892bf5726df37d0c6e2 | |
| parent | 998f7cb29af596f523b8d8b90c968ebd7e8dc178 (diff) | |
| download | u-boot-a89441a74f6df1f75b942f6906724620fad2e8e1.tar.gz | |
arm: socfpga: gen5: don't zero bss in board_init_f()
The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
DDR driver does not use bss any more, bss is not used before board_init_r()
and we can remove this hack.
bss is normally zeroed by crt0.S, but after board_init_f(), before
board_init_r(). socfpga just had this double-zeroing because it invalidly
used bss in board_init_f() already (during DDR initialization).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| -rw-r--r-- | arch/arm/mach-socfpga/spl_gen5.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 87b76b47de..47e63709ad 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -79,8 +79,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); - memset(__bss_start, 0, __bss_end - __bss_start); - socfpga_sdram_remap_zero(); socfpga_pl310_clear(); |