Merge tag 'xilinx-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
author: Tom Rini <trini@konsulko.com> 2020-01-16 09:45:40 -0500
committer: Tom Rini <trini@konsulko.com> 2020-01-16 09:45:40 -0500
commit: 92329e2413f444d1edf29bab66aefccfd782e0a7 (patch)
tree: f8d5b354b1f228a5258ba01ca801b8e3a5d31792
parent: f47704d4ae494ebc8a25c95202e548ea32f98955 (diff)
parent: ddb55ff8a66dabe3365735eff9f901bb259c223f (diff)
download: u-boot-92329e2413f444d1edf29bab66aefccfd782e0a7.tar.gz
119 files changed, 1677 insertions, 3899 deletions
diff --git a/Kconfig b/Kconfig
index 99cc56f3c2..d9be0daf23 100644
--- a/Kconfig
+++ b/Kconfig
@@ -254,7 +254,7 @@ config BUILD_TARGET
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
 	default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV)
+				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
@@ -500,6 +500,7 @@ config SPL_FIT_GENERATOR
 	depends on SPL_FIT
 	default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
 	default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
+	default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
 	default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
 	help
 	  Specifies a (platform specific) script file to generate the FIT
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee3ca8d182..a623ef5743 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARM64
 if ARM64
 config POSITION_INDEPENDENT
 	bool "Generate position-independent pre-relocation code"
+	select INIT_SP_RELATIVE
 	help
 	  U-Boot expects to be linked to a specific hard-coded address, and to
 	  be loaded to and run from that address. This option lifts that
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index adb843c885..04a8cccda5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -282,6 +282,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zcu111-revA.dtb			\
 	zynqmp-zcu1275-revA.dtb			\
 	zynqmp-zcu1275-revB.dtb			\
+	zynqmp-zcu1285-revA.dtb			\
+	zynqmp-zcu208-revA.dtb			\
 	zynqmp-zcu216-revA.dtb			\
 	zynqmp-zc1232-revA.dtb			\
 	zynqmp-zc1254-revA.dtb			\
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 07dfa0d107..c35eb2344f 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -62,6 +62,39 @@
 		regulator-always-on;
 	};
 
+	replicator {
+		compatible = "arm,coresight-static-replicator";
+		clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+		clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* replicator output ports */
+			port@0 {
+				reg = <0>;
+				replicator_out_port0: endpoint {
+					remote-endpoint = <&tpiu_in_port>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				replicator_out_port1: endpoint {
+					remote-endpoint = <&etb_in_port>;
+				};
+			};
+		};
+		in-ports {
+			/* replicator input port */
+			port {
+				replicator_in_port0: endpoint {
+					remote-endpoint = <&funnel_out_port>;
+				};
+			};
+		};
+	};
+
 	amba: amba {
 		u-boot,dm-pre-reloc;
 		compatible = "simple-bus";
@@ -415,5 +448,107 @@
 			reg = <0xf8005000 0x1000>;
 			timeout-sec = <10>;
 		};
+
+		etb@f8801000 {
+			compatible = "arm,coresight-etb10", "arm,primecell";
+			reg = <0xf8801000 0x1000>;
+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+			in-ports {
+				port {
+					etb_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port1>;
+					};
+				};
+			};
+		};
+
+		tpiu@f8803000 {
+			compatible = "arm,coresight-tpiu", "arm,primecell";
+			reg = <0xf8803000 0x1000>;
+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+			in-ports {
+				port {
+					tpiu_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port0>;
+					};
+				};
+			};
+		};
+
+		funnel@f8804000 {
+			compatible = "arm,coresight-static-funnel", "arm,primecell";
+			reg = <0xf8804000 0x1000>;
+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+			/* funnel output ports */
+			out-ports {
+				port {
+					funnel_out_port: endpoint {
+						remote-endpoint =
+							<&replicator_in_port0>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* funnel input ports */
+				port@0 {
+					reg = <0>;
+					funnel0_in_port0: endpoint {
+						remote-endpoint = <&ptm0_out_port>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					funnel0_in_port1: endpoint {
+						remote-endpoint = <&ptm1_out_port>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					funnel0_in_port2: endpoint {
+					};
+				};
+				/* The other input ports are not connect to anything */
+			};
+		};
+
+		ptm@f889c000 {
+			compatible = "arm,coresight-etm3x", "arm,primecell";
+			reg = <0xf889c000 0x1000>;
+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+			cpu = <&cpu0>;
+			out-ports {
+				port {
+					ptm0_out_port: endpoint {
+						remote-endpoint = <&funnel0_in_port0>;
+					};
+				};
+			};
+		};
+
+		ptm@f889d000 {
+			compatible = "arm,coresight-etm3x", "arm,primecell";
+			reg = <0xf889d000 0x1000>;
+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+			cpu = <&cpu1>;
+			out-ports {
+				port {
+					ptm1_out_port: endpoint {
+						remote-endpoint = <&funnel0_in_port1>;
+					};
+				};
+			};
+		};
 	};
 };
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 1123bfc743..61482017d6 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -47,6 +47,14 @@
 	};
 };
 
+&nand0 {
+	status = "okay";
+};
+
+&smcc {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	num-cs = <4>;
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 998298cc9b..8eacd22d7c 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -2,7 +2,7 @@
 /*
  * Clock specification for Xilinx ZynqMP
  *
- * (C) Copyright 2017, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -173,26 +173,30 @@
 };
 
 &gem0 {
-	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,
-		 <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;
+	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
+		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
+		 <&zynqmp_clk GEM_TSU>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem1 {
-	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,
-		 <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;
+	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+		 <&zynqmp_clk GEM_TSU>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem2 {
-	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,
-		 <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;
+	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
+		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
+		 <&zynqmp_clk GEM_TSU>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem3 {
-	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,
-		 <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;
+	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
+		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+		 <&zynqmp_clk GEM_TSU>;
 	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index 9ef55ad0d1..c9464ec8eb 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -61,13 +61,13 @@
 		clock-accuracy = <100>;
 	};
 
-	dpdma_clk: dpdma_clk {
+	dpdma_clk: dpdma-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0x0>;
 		clock-frequency = <533000000>;
 	};
 
-	drm_clock: drm_clock {
+	drm_clock: drm-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0x0>;
 		clock-frequency = <262750000>;
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index 93aa193f01..d376ade834 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -50,55 +50,6 @@
 			#size-cells = <1>;
 			arasan,has-mdma;
 			num-cs = <2>;
-
-			partition@0 {	/* for testing purpose */
-				label = "nand-fsbl-uboot";
-				reg = <0x0 0x0 0x400000>;
-			};
-			partition@1 {	/* for testing purpose */
-				label = "nand-linux";
-				reg = <0x0 0x400000 0x1400000>;
-			};
-			partition@2 {	/* for testing purpose */
-				label = "nand-device-tree";
-				reg = <0x0 0x1800000 0x400000>;
-			};
-			partition@3 {	/* for testing purpose */
-				label = "nand-rootfs";
-				reg = <0x0 0x1C00000 0x1400000>;
-			};
-			partition@4 {	/* for testing purpose */
-				label = "nand-bitstream";
-				reg = <0x0 0x3000000 0x400000>;
-			};
-			partition@5 {	/* for testing purpose */
-				label = "nand-misc";
-				reg = <0x0 0x3400000 0xFCC00000>;
-			};
-			partition@6 {	/* for testing purpose */
-				label = "nand1-fsbl-uboot";
-				reg = <0x1 0x0 0x400000>;
-			};
-			partition@7 {	/* for testing purpose */
-				label = "nand1-linux";
-				reg = <0x1 0x400000 0x1400000>;
-			};
-			partition@8 {	/* for testing purpose */
-				label = "nand1-device-tree";
-				reg = <0x1 0x1800000 0x400000>;
-			};
-			partition@9 {	/* for testing purpose */
-				label = "nand1-rootfs";
-				reg = <0x1 0x1C00000 0x1400000>;
-			};
-			partition@10 {	/* for testing purpose */
-				label = "nand1-bitstream";
-				reg = <0x1 0x3000000 0x400000>;
-			};
-			partition@11 {	/* for testing purpose */
-				label = "nand1-misc";
-				reg = <0x1 0x3400000 0xFCC00000>;
-			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 14aa98de73..21118c8cc3 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -53,7 +53,7 @@
 			label = "sw4";
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 			autorepeat;
 		};
 	};
@@ -95,7 +95,7 @@
 			linux,default-trigger = "bluetooth-power";
 		};
 
-		vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+		vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
 			label = "vbus_det";
 			gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
@@ -120,9 +120,10 @@
 		regulator-boot-on;
 	};
 
-	sdio_pwrseq: sdio_pwrseq {
+	sdio_pwrseq: sdio-pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+		post-power-on-delay-ms = <10>;
 	};
 
 	ina226 {
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 78110c490e..b580f9263d 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -51,14 +51,14 @@
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
-			gpio-key,wakeup;
+			wakeup-source;
 			autorepeat;
 		};
 	};
 
 	leds {
 		compatible = "gpio-leds";
-		heartbeat_led {
+		heartbeat-led {
 			label = "heartbeat";
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -213,25 +213,25 @@
 		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
 				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
 				"", "", "", "", "", "", "", "", "";
-		gtr_sel0 {
+		gtr-sel0 {
 			gpio-hog;
 			gpios = <0 0>;
 			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
-		gtr_sel1 {
+		gtr-sel1 {
 			gpio-hog;
 			gpios = <1 0>;
 			output-high; /* PCIE = 0, DP = 1 */
 			line-name = "sel1";
 		};
-		gtr_sel2 {
+		gtr-sel2 {
 			gpio-hog;
 			gpios = <2 0>;
 			output-high; /* PCIE = 0, USB0 = 1 */
 			line-name = "sel2";
 		};
-		gtr_sel3 {
+		gtr-sel3 {
 			gpio-hog;
 			gpios = <3 0>;
 			output-high; /* PCIE = 0, SATA = 1 */
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 2132024a25..38ec188164 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -25,7 +25,7 @@
 		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
 	};
 	/* Cleanup from RevA */
-	/delete-node/ phy@21;
+	/delete-node/ ethernet-phy@21;
 };
 
 /* Fix collision with u61 */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index b4dd101330..d31982fce7 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -51,14 +51,14 @@
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
-			gpio-key,wakeup;
+			wakeup-source;
 			autorepeat;
 		};
 	};
 
 	leds {
 		compatible = "gpio-leds";
-		heartbeat_led {
+		heartbeat-led {
 			label = "heartbeat";
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -653,7 +653,6 @@
 /* SD1 with level shifter */
 &sdhci1 {
 	status = "okay";
-	no-1-8-v;
 	xlnx,mio_bank = <1>;
 };
 
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index aabf73dd6d..bff224f78d 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -51,14 +51,14 @@
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
-			gpio-key,wakeup;
+			wakeup-source;
 			autorepeat;
 		};
 	};
 
 	leds {
 		compatible = "gpio-leds";
-		heartbeat_led {
+		heartbeat-led {
 			label = "heartbeat";
 			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -566,7 +566,6 @@
 /* SD1 with level shifter */
 &sdhci1 {
 	status = "okay";
-	no-1-8-v;
 	disable-wp;
 	xlnx,mio_bank = <1>;
 };
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index 34c4becd43..2ec29b0b5d 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -75,6 +75,10 @@
 
 &sdhci1 {
 	status = "okay";
+	/*
+	 * 1.0 revision has level shifter and this property should be
+	 * removed for supporting UHS mode
+	 */
 	no-1-8-v;
 	xlnx,mio_bank = <1>;
 };
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
new file mode 100644
index 0000000000..9c18013138
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU1285 RevA
+ *
+ * (C) Copyright 2018 - 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+	model = "ZynqMP ZCU1285 RevA";
+	compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
+		     "xlnx,zynqmp";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &dcc;
+		spi0 = &qspi;
+		mmc0 = &sdhci1;
+		i2c = &i2c0; /* EMIO */
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	ina226-u60 {
+		compatible = "iio-hwmon";
+		io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
+	};
+	ina226-u61 {
+		compatible = "iio-hwmon";
+		io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
+	};
+	ina226-u63 {
+		compatible = "iio-hwmon";
+		io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
+	};
+	ina226-u65 {
+		compatible = "iio-hwmon";
+		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
+	};
+	ina226-u64 {
+		compatible = "iio-hwmon";
+		io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
+	};
+};
+
+&dcc {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	i2c-mux@75 {
+		compatible = "nxp,pca9548"; /* u22 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* PMBUS */
+			max20751@74 { /* u23 */
+				compatible = "maxim,max20751";
+				reg = <0x74>;
+			};
+			max20751@70 { /* u89 */
+				compatible = "maxim,max20751";
+				reg = <0x70>;
+			};
+			max15301@a { /* u28 */
+				compatible = "maxim,max15301";
+				reg = <0xa>;
+			};
+			max15303@b { /* u48 */
+				compatible = "maxim,max15303";
+				reg = <0xb>;
+			};
+			max15303@d { /* u27 */
+				compatible = "maxim,max15303";
+				reg = <0xd>;
+			};
+			max15303@e { /* u11 */
+				compatible = "maxim,max15303";
+				reg = <0xe>;
+			};
+			max15303@f { /* u96 */
+				compatible = "maxim,max15303";
+				reg = <0xf>;
+			};
+			max15303@11 { /* u47 */
+				compatible = "maxim,max15303";
+				reg = <0x11>;
+			};
+			max15303@12 { /* u24 */
+				compatible = "maxim,max15303";
+				reg = <0x12>;
+			};
+			max15301@13 { /* u29 */
+				compatible = "maxim,max15301";
+				reg = <0x13>;
+			};
+			max15303@14 { /* u51 */
+				compatible = "maxim,max15303";
+				reg = <0x14>;
+			};
+			max15303@15 { /* u30 */
+				compatible = "maxim,max15303";
+				reg = <0x15>;
+			};
+			max15303@16 { /* u102 */
+				compatible = "maxim,max15303";
+				reg = <0x16>;
+			};
+			max15301@17 { /* u50 */
+				compatible = "maxim,max15301";
+				reg = <0x17>;
+			};
+			max15301@18 { /* u31 */
+				compatible = "maxim,max15301";
+				reg = <0x18>;
+			};
+		};
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* CM_I2C */
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* SYS_EEPROM */
+			eeprom: eeprom@54 { /* u101 */
+				compatible = "atmel,24c32"; /* 24LC32A */
+				reg = <0x54>;
+			};
+		};
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* FMC1 */
+		};
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* FMC2 */
+		};
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* ANALOG_PMBUS */
+			u60: ina226@40 { /* u60 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-u60";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+			u61: ina226@41 { /* u61 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-u61";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+			u63: ina226@42 { /* u63 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-u63";
+				reg = <0x42>;
+				shunt-resistor = <1000>;
+			};
+			u65: ina226@43 { /* u65 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-u65";
+				reg = <0x43>;
+				shunt-resistor = <1000>;
+			};
+			u64: ina226@44 { /* u64 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-u64";
+				reg = <0x44>;
+				shunt-resistor = <1000>;
+			};
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			/* ANALOG_CM_I2C */
+		};
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			/* FMC3 */
+		};
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&sdhci1 {
+	status = "okay";
+	xlnx,mio_bank = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
new file mode 100644
index 0000000000..9181060b89
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU208
+ *
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+	model = "ZynqMP ZCU208 RevA";
+	compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &dcc;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = &eeprom;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		sw19 {
+			label = "sw19";
+			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_DOWN>;
+			gpio-key,wakeup;
+			autorepeat;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		heartbeat_led {
+			label = "heartbeat";
+			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	ina226-vccint {
+		compatible = "iio-hwmon";
+		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
+	};
+	ina226-vccint-io-bram-ps {
+		compatible = "iio-hwmon";
+		io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
+	};
+	ina226-vcc1v8 {
+		compatible = "iio-hwmon";
+		io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
+	};
+	ina226-vcc1v2 {
+		compatible = "iio-hwmon";
+		io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
+	};
+	ina226-vadj-fmc {
+		compatible = "iio-hwmon";
+		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
+	};
+	ina226-mgtavcc {
+		compatible = "iio-hwmon";
+		io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
+	};
+	ina226-mgt1v2 {
+		compatible = "iio-hwmon";
+		io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
+	};
+	ina226-mgt1v8 {
+		compatible = "iio-hwmon";
+		io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
+	};
+	ina226-vccint-ams {
+		compatible = "iio-hwmon";
+		io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
+	};
+	ina226-dac-avtt {
+		compatible = "iio-hwmon";
+		io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
+	};
+	ina226-dac-avccaux {
+		compatible = "iio-hwmon";
+		io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
+	};
+	ina226-adc-avcc {
+		compatible = "iio-hwmon";
+		io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
+	};
+	ina226-adc-avccaux {
+		compatible = "iio-hwmon";
+		io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
+	};
+	ina226-dac-avcc {
+		compatible = "iio-hwmon";
+		io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
+	};
+};
+
+&dcc {
+	status = "okay";
+};
+
+&fpd_dma_chan1 {
+	status = "okay";
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+};
+
+&gem3 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: ethernet-phy@c {
+		reg = <0xc>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+		ti,dp83867-rxctrl-strap-quirk;
+	};
+};
+
+&gpio {
+	status = "okay";
+	gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
+		  "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
+		  "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
+		  "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
+		  "", "", "BUTTON", "LED", "", /* 20 - 24 */
+		  "", "PMU_INPUT", "", "", "", /* 25 - 29 */
+		  "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
+		  "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
+		  "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
+		  "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
+		  "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
+		  "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
+		  "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
+		  "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
+		  "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
+		  "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
+		  "", "", /* 78 - 79 */
+		  "", "", "", "", "", /* 80 - 84 */
+		  "", "", "", "", "", /* 85 -89 */
+		  "", "", "", "", "", /* 90 - 94 */
+		  "", "", "", "", "", /* 95 - 99 */
+		  "", "", "", "", "", /* 100 - 104 */
+		  "", "", "", "", "", /* 105 - 109 */
+		  "", "", "", "", "", /* 110 - 114 */
+		  "", "", "", "", "", /* 115 - 119 */
+		  "", "", "", "", "", /* 120 - 124 */
+		  "", "", "", "", "", /* 125 - 129 */
+		  "", "", "", "", "", /* 130 - 134 */
+		  "", "", "", "", "", /* 135 - 139 */
+		  "", "", "", "", "", /* 140 - 144 */
+		  "", "", "", "", "", /* 145 - 149 */
+		  "", "", "", "", "", /* 150 - 154 */
+		  "", "", "", "", "", /* 155 - 159 */
+		  "", "", "", "", "", /* 160 - 164 */
+		  "", "", "", "", "", /* 165 - 169 */
+		  "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u15: gpio@20 { /* u15 */
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller; /* interrupt not connected */
+		#gpio-cells = <2>;
+		gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
+				  "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
+				  "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
+				  "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
+	};
+
+	i2c-mux@75 { /* u17 */
+		compatible = "nxp,pca9544";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* PS_PMBUS */
+			/* PMBUS_ALERT done via pca9544 */
+			vccint: ina226@40 { /* u65 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vccint";
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
+			vccint_io_bram_ps: ina226@41 { /* u57 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vccint-io-bram-ps";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			vcc1v8: ina226@42 { /* u60 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vcc1v8";
+				reg = <0x42>;
+				shunt-resistor = <2000>;
+			};
+			vcc1v2: ina226@43 { /* u58 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vcc1v2";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			vadj_fmc: ina226@45 { /* u62 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vadj-fmc";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			mgtavcc: ina226@46 { /* u67 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-mgtavcc";
+				reg = <0x46>;
+				shunt-resistor = <2000>;
+			};
+			mgt1v2: ina226@47 { /* u63 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-mgt1v2";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+			mgt1v8: ina226@48 { /* u64 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-mgt1v8";
+				reg = <0x48>;
+				shunt-resistor = <5000>;
+			};
+			vccint_ams: ina226@49 { /* u61 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-vccint-ams";
+				reg = <0x49>;
+				shunt-resistor = <5000>;
+			};
+			dac_avtt: ina226@4a { /* u59 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-dac-avtt";
+				reg = <0x4a>;
+				shunt-resistor = <5000>;
+			};
+			dac_avccaux: ina226@4b { /* u124 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-dac-avccaux";
+				reg = <0x4b>;
+				shunt-resistor = <5000>;
+			};
+			adc_avcc: ina226@4c { /* u75 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-adc-avcc";
+				reg = <0x4c>;
+				shunt-resistor = <5000>;
+			};
+			adc_avccaux: ina226@4d { /* u71 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-adc-avccaux";
+				reg = <0x4d>;
+				shunt-resistor = <5000>;
+			};
+			dac_avcc: ina226@4e { /* u77 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				label = "ina226-dac-avcc";
+				reg = <0x4e>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* NC */
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* u104 - ir35215 0x10/0x40 */
+			/* u127 - ir38164 0x1b/0x4b */
+			/* u112 - ir38164 0x13/0x43 */
+			/* u123 - ir38164 0x1c/0x4c */
+
+			irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
+				#clock-cells = <0>;
+				compatible = "infineon,irps5401";
+				reg = <0x44>; /* i2c addr 0x14 */
+			};
+			irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
+				#clock-cells = <0>;
+				compatible = "infineon,irps5401";
+				reg = <0x45>; /* i2c addr 0x15 */
+			};
+			/* J21 header too */
+
+		};
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* SYSMON */
+		};
+	};
+	/* u38 MPS430 */
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	i2c-mux@74 {
+		compatible = "nxp,pca9548"; /* u20 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+		i2c_eeprom: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/*
+			 * IIC_EEPROM 1kB memory which uses 256B blocks
+			 * where every block has different address.
+			 *    0 - 256B address 0x54
+			 * 256B - 512B address 0x55
+			 * 512B - 768B address 0x56
+			 * 768B - 1024B address 0x57
+			 */
+			eeprom: eeprom@54 { /* u21 */
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+		i2c_si5341: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			si5341: clock-generator@36 { /* SI5341 - u43 */
+				compatible = "si5341";
+				reg = <0x36>;
+			};
+
+		};
+		i2c_si570_user_c0: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>;
+				clock-frequency = <300000000>;
+				clock-output-names = "si570_user_c0";
+			};
+		};
+		i2c_si570_mgt: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <156250000>;
+				clock-frequency = <148500000>;
+				clock-output-names = "si570_mgt";
+			};
+		};
+		i2c_8a34001: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* U409B - 8a34001 */
+		};
+		i2c_clk104: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* CLK104_SDA */
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			/* RFMCP connector */
+		};
+		/* 7 NC */
+	};
+
+	i2c-mux@75 {
+		compatible = "nxp,pca9548"; /* u22 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* FMCP_HSPC_IIC */
+		};
+		i2c_si570_user_c1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>;
+				clock-frequency = <300000000>;
+				clock-output-names = "si570_user_c1";
+			};
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* SYSMON */
+		};
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* DDR4 SODIMM */
+		};
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* SFP3 */
+		};
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* SFP2 */
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			/* SFP1 */
+		};
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			/* SFP0 */
+		};
+	};
+	/* MSP430 */
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <1>;
+	flash@0 {
+		compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+	/* SATA OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	disable-wp;
+	xlnx,mio_bank = <1>;
+};
+
+&serdes {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index dd9cd7b38f..c294e1b51a 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -253,7 +253,7 @@
 				#io-channel-cells = <1>;
 				label = "ina226-vccint-io-bram-ps";
 				reg = <0x41>;
-				shunt-resistor = <2000>;
+				shunt-resistor = <5000>;
 			};
 			vcc1v8: ina226@42 { /* u60 */
 				compatible = "ti,ina226";
@@ -302,7 +302,7 @@
 				#io-channel-cells = <1>;
 				label = "ina226-vccint-ams";
 				reg = <0x49>;
-				shunt-resistor = <2000>;
+				shunt-resistor = <5000>;
 			};
 			dac_avtt: ina226@4a { /* u59 */
 				compatible = "ti,ina226";
@@ -401,7 +401,7 @@
 			 * 768B - 1024B address 0x57
 			 */
 			eeprom: eeprom@54 { /* u21 */
-				compatible = "atmel,24c08";
+				compatible = "atmel,24c128";
 				reg = <0x54>;
 			};
 		};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b453941baf..9e7fae83f7 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -25,7 +25,7 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			operating-points-v2 = <&cpu_opp_table>;
@@ -34,7 +34,7 @@
 		};
 
 		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x1>;
@@ -43,7 +43,7 @@
 		};
 
 		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x2>;
@@ -52,7 +52,7 @@
 		};
 
 		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
+			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x3>;
@@ -74,7 +74,7 @@
 		};
 	};
 
-	cpu_opp_table: cpu_opp_table {
+	cpu_opp_table: cpu-opp-table {
 		compatible = "operating-points-v2";
 		opp-shared;
 		opp00 {
@@ -252,7 +252,7 @@
 		};
 	};
 
-	amba_apu: amba_apu@0 {
+	amba_apu: amba-apu@0 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
@@ -626,12 +626,12 @@
 			compatible = "xlnx,zynqmp-gpio-1.0";
 			status = "disabled";
 			#gpio-cells = <0x2>;
+			gpio-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <0 16 4>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			reg = <0x0 0xff0a0000 0x0 0x1000>;
-			gpio-controller;
 			power-domains = <&zynqmp_firmware PD_GPIO>;
 		};
 
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index 5412ed6827..89eb565c94 100644
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -9,13 +9,8 @@
 #define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
 #define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
 #define ZYNQ_SCU_BASEADDR		0xF8F00000
-#define ZYNQ_QSPI_BASEADDR		0xE000D000
-#define ZYNQ_SMC_BASEADDR		0xE000E000
-#define ZYNQ_NAND_BASEADDR		0xE1000000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 #define ZYNQ_EFUSE_BASEADDR		0xF800D000
-#define ZYNQ_USB_BASEADDR0		0xE0002000
-#define ZYNQ_USB_BASEADDR1		0xE0003000
 #define ZYNQ_OCM_BASEADDR		0xFFFC0000
 
 /* Bootmode setting values */
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 6cf17eb94e..d82a737a69 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
 config ZYNQ_SDHCI_MAX_FREQ
 	default 200000000
 
-config SPL_ZYNQMP_TWO_SDHCI
-	bool "Enable booting from both SDHCIs"
-	depends on SPL
-	help
-	  This option reflects that board has two SDHCI controllers which
-	  platform can use as boot device. This option ensures that SPL will
-	  setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
-	  SDHCI0 controller. Platforms which have only one SDHCI controller
-	  shouldn't enable this option because it for software SDHCI0 or SDHCI1
-	  are both covered by BOOT_DEVICE_MMC1.
-
 config SPL_ZYNQMP_ALT_BOOTMODE
 	hex
 	default 0x0 if JTAG_MODE
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index f71ff7b3d2..64e5320acc 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -66,7 +66,9 @@ struct xfsbl_atf_handoff_params {
 };
 
 #ifdef CONFIG_SPL_OS_BOOT
-void handoff_setup(void)
+struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
+					     uintptr_t bl33_entry,
+					     uintptr_t fdt_addr)
 {
 	struct xfsbl_atf_handoff_params *atfhandoffparams;
 
@@ -76,11 +78,16 @@ void handoff_setup(void)
 	atfhandoffparams->magic[2] = 'N';
 	atfhandoffparams->magic[3] = 'X';
 
-	atfhandoffparams->num_entries = 1;
-	atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE;
-	atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
-					       FSBL_FLAGS_EL_SHIFT;
+	atfhandoffparams->num_entries = 0;
+	if (bl33_entry) {
+		atfhandoffparams->partition[0].entry_point = bl33_entry;
+		atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
+						       FSBL_FLAGS_EL_SHIFT;
+		atfhandoffparams->num_entries++;
+	}
 
 	writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
+
+	return NULL;
 }
 #endif
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index a0d776166d..fd361c5ce8 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-#define ARASAN_NAND_BASEADDR	0xFF100000
-
 #define ZYNQMP_TCM_BASE_ADDR	0xFFE00000
 #define ZYNQMP_TCM_SIZE		0x40000
 
diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
index 15e54c0493..e37acda2f8 100644
--- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
+++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
@@ -21,5 +21,6 @@ void prog_reg(unsigned long addr, unsigned long mask,
 	      unsigned long shift, unsigned long value);
 
 int psu_init(void);
+unsigned long psu_post_config_data(void);
 
 #endif /* _PSU_INIT_GPL_H_ */
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 10b70761de..2974ffbc2f 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -46,8 +46,6 @@ struct zynqmp_ipi_msg {
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 unsigned int zynqmp_get_silicon_version(void);
 
-void handoff_setup(void);
-
 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
 int zynqmp_mmio_read(const u32 address, u32 *value);
 
diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
new file mode 100755
index 0000000000..1e770ba111
--- /dev/null
+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
@@ -0,0 +1,123 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for Xilinx ZynqMP boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+BL33="u-boot-nodtb.bin"
+[ -z "$BL31" ] && BL31="bl31.bin"
+# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }'
+[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000"
+
+if [ -z "$BL33_LOAD_ADDR" ];then
+	BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h`
+fi
+
+DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h`
+if [ ! -z "$DTB_LOAD_ADDR" ]; then
+	DTB_LOAD="load = <$DTB_LOAD_ADDR>;"
+else
+	DTB_LOAD=""
+fi
+
+if [ -z "$*" ]; then
+	DT=arch/arm/dts/${DEVICE_TREE}.dtb
+else
+	DT=$*
+fi
+
+if [ ! -f $BL31 ]; then
+	echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
+	BL31=/dev/null
+	# But U-Boot proper could be loaded in EL3 by specifying
+	# firmware = "uboot";
+	# instead of "atf" in config node
+fi
+
+cat << __HEADER_EOF
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/dts-v1/;
+
+/ {
+	description = "Configuration to load ATF before U-Boot";
+
+	images {
+		uboot {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("$BL33");
+			type = "firmware";
+			os = "u-boot";
+			arch = "arm64";
+			compression = "none";
+			load = <$BL33_LOAD_ADDR>;
+			entry = <$BL33_LOAD_ADDR>;
+			hash {
+				algo = "md5";
+			};
+		};
+		atf {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("$BL31");
+			type = "firmware";
+			os = "arm-trusted-firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <$ATF_LOAD_ADDR>;
+			entry = <$ATF_LOAD_ADDR>;
+			hash {
+				algo = "md5";
+			};
+		};
+__HEADER_EOF
+
+DEFAULT=1
+cnt=1
+for dtname in $DT
+do
+	cat << __FDT_IMAGE_EOF
+		fdt_$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			$DTB_LOAD
+			hash {
+				algo = "md5";
+			};
+		};
+__FDT_IMAGE_EOF
+
+[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt
+
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+	};
+	configurations {
+		default = "config_$DEFAULT";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $DT
+do
+cat << __CONF_SECTION1_EOF
+		config_$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "atf";
+			loadables = "uboot";
+			fdt = "fdt_$cnt";
+		};
+__CONF_SECTION1_EOF
+cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+	};
+};
+__ITS_EOF
diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c
index b357de3235..b6abdfd608 100644
--- a/arch/arm/mach-zynqmp/psu_spl_init.c
+++ b/arch/arm/mach-zynqmp/psu_spl_init.c
@@ -77,3 +77,12 @@ __weak int psu_init(void)
 	 */
 	return -1;
 }
+
+__weak unsigned long psu_post_config_data(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 6ba42bb42f..896657f51c 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/spl.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/psu_init_gpl.h>
 #include <asm/arch/sys_proto.h>
 
 void board_init_f(ulong dummy)
@@ -27,13 +28,6 @@ void board_init_f(ulong dummy)
 #endif
 	/* Delay is required for clocks to be propagated */
 	udelay(1000000);
-
-	debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
-	/* Clear the BSS */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* No need to call timer init - it is empty for ZynqMP */
-	board_init_r(NULL, 0);
 }
 
 static void ps_mode_reset(ulong mode)
@@ -60,9 +54,20 @@ void spl_board_init(void)
 	preloader_console_init();
 	ps_mode_reset(MODE_RESET);
 	board_init();
+	psu_post_config_data();
 }
 #endif
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
+		spl_boot_list[1] = BOOT_DEVICE_MMC2;
+	if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
 u32 spl_boot_device(void)
 {
 	u32 reg = 0;
@@ -86,11 +91,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case SD_MODE1:
 	case SD1_LSHFT_MODE: /* not working on silicon v1 */
-/* if both controllers enabled, then these two are the second controller */
-#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
 		return BOOT_DEVICE_MMC2;
-/* else, fall through, the one SDHCI controller that is enabled is number 1 */
-#endif
 	case SD_MODE:
 	case EMMC_MODE:
 		return BOOT_DEVICE_MMC1;
@@ -119,8 +120,6 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
-	handoff_setup();
-
 	return 0;
 }
 #endif
@@ -131,6 +130,6 @@ int board_fit_config_name_match(const char *name)
 	/* Just empty function now - can't decide what to choose */
 	debug("%s: %s\n", __func__, name);
 
-	return 0;
+	return -1;
 }
 #endif
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 500dcce4da..80f2b83b58 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0XF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
index 8be3fb1e35..360beaef8e 100644
--- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
index afec4038d3..ae4666f7d5 100644
--- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
index d90a350d3f..717955808d 100644
--- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index cb272eafda..73fc1be014 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -44,6 +44,15 @@ config XILINX_OF_BOARD_DTB_ADDR
 	hex
 	default 0x1000 if ARCH_VERSAL
 	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
-	depends on OF_BOARD
+	depends on OF_BOARD || OF_SEPARATE
 	help
 	  Offset in the memory where the board configuration DTB is placed.
+
+config BOOT_SCRIPT_OFFSET
+	hex "Boot script offset"
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
+	default 0xFC0000 if ARCH_ZYNQ
+	default 0x3E80000 if ARCH_ZYNQMP
+	default 0x7F80000 if ARCH_VERSAL
+	help
+	   Specifies distro boot script offset in NAND/NOR flash.
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 1c28263cb8..ae5fe2729f 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/sections.h>
 #include <dm/uclass.h>
 #include <i2c.h>
 
@@ -37,16 +38,32 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 	return ret;
 }
 
-#if defined(CONFIG_OF_BOARD)
+#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
 void *board_fdt_blob_setup(void)
 {
-	static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+	static void *fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
 
-	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
-		printf("DTB is not passed via %p\n", fw_dtb);
-		return NULL;
-	}
+	if (fdt_magic(fdt_blob) == FDT_MAGIC)
+		return fdt_blob;
 
-	return fw_dtb;
+	debug("DTB is not passed via %p\n", fdt_blob);
+
+#ifdef CONFIG_SPL_BUILD
+	/* FDT is at end of BSS unless it is in a different memory region */
+	if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+		fdt_blob = (ulong *)&_image_binary_end;
+	else
+		fdt_blob = (ulong *)&__bss_end;
+#else
+	/* FDT is at end of image */
+	fdt_blob = (ulong *)&_end;
+#endif
+
+	if (fdt_magic(fdt_blob) == FDT_MAGIC)
+		return fdt_blob;
+
+	debug("DTB is also not passed via %p\n", fdt_blob);
+
+	return NULL;
 }
 #endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 23bb6b9623..9fa9e76e66 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -130,7 +130,14 @@ int board_late_init(void)
 		break;
 	case EMMC_MODE:
 		puts("EMMC_MODE\n");
-		mode = "mmc0";
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from EMMC but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
+		mode = "mmc";
+		bootseq = dev->seq;
 		break;
 	case SD_MODE:
 		puts("SD_MODE\n");
@@ -196,6 +203,8 @@ int board_late_init(void)
 	initrd_hi = round_down(initrd_hi, SZ_16M);
 	env_set_addr("initrd_high", (void *)initrd_hi);
 
+	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
 	return 0;
 }
 
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 8d33015439..6a2acee108 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -14,7 +14,7 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
 endif
 
 ifeq ($(init-objs),)
-hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
 	$(hw-platform-y)/ps7_init_gpl.o)
 endif
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index cffabe825a..420a5ca663 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -50,7 +50,7 @@ int board_late_init(void)
 		env_set("modeboot", "sdboot");
 		break;
 	case ZYNQ_BM_JTAG:
-		mode = "pxe dhcp";
+		mode = "jtag pxe dhcp";
 		env_set("modeboot", "jtagboot");
 		break;
 	default:
@@ -76,6 +76,8 @@ int board_late_init(void)
 
 	env_set("boot_targets", new_targets);
 
+	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
 	return 0;
 }
 
diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
index 218307f861..82f270c2e1 100644
--- a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
@@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
@@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
index 5366956e5b..75095ee3d4 100644
--- a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
@@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index 39afd82195..337af2d964 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index 88ff7947f2..248c72861c 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index e9e4e4d077..c84ee6b1f2 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
index 95cc25a03e..b4663818dd 100644
--- a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
index 209f5ed7aa..254a512ccb 100644
--- a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
index 31c497b3e6..f4362b943b 100644
--- a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
index e966304e4a..621de09cc6 100644
--- a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
index 5770c4d5d3..eefd46d932 100644
--- a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index df7d3535dd..7a15ea5729 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
index d4f0ee796f..5d573868cb 100644
--- a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
@@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
index f1b9357780..7c6bc9fa3f 100644
--- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index c41283704c..fda6d18dd9 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 5ace6cc1b4..174f4ed24b 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -14,7 +14,7 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
 endif
 
 ifeq ($(init-objs),)
-hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
 	$(hw-platform-y)/psu_init_gpl.o)
 endif
diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
index ac3f716392..d030e79770 100644
--- a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
@@ -506,14 +506,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
index ac4a073e1b..be9992c90f 100644
--- a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
@@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
index a64c140b86..a64c140b86 120000
--- a/board/xilinx/zynqmp/zynqmp-a2197-g-revA
+++ b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
index a64c140b86..a64c140b86 120000
--- a/board/xilinx/zynqmp/zynqmp-a2197-m-revA
+++ b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
index a64c140b86..a64c140b86 120000
--- a/board/xilinx/zynqmp/zynqmp-a2197-p-revA
+++ b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
diff --git a/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
new file mode 120000
index 0000000000..a64c140b86
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
+\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
new file mode 120000
index 0000000000..a64c140b86
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
+\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
index af6b49a973..b8ea291f8b 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
@@ -388,10 +388,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
index a5a33b9f17..520fff28f9 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
@@ -378,10 +378,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
 	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c
index d1090fae4a..d3eb713e9e 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c
@@ -427,10 +427,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
index f73e997f7d..6b0705df38 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -475,10 +475,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
index 9ead77d069..59de4373b6 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
index 9ead77d069..59de4373b6 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
index 9ead77d069..59de4373b6 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
index db07456c15..e0b71abd51 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -471,14 +471,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
index e1fdabaeb9..e01915f7ed 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
@@ -409,7 +409,6 @@ static unsigned long psu_mio_init_data(void)
 	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
 	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
 	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
-	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
 	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
 	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
 	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
@@ -499,14 +498,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
 	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
@@ -990,3 +981,9 @@ int psu_init(void)
 		return 1;
 	return 0;
 }
+
+unsigned long psu_post_config_data(void)
+{
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
index 3e981d8419..6adbf5e234 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
@@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
index 5f21c47475..8ecd9ee90b 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -486,14 +486,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U);
 	psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U);
 	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
 	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
index 12ef5b4b0a..4805e5a3b9 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -455,14 +455,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
 	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
index fcd6a46ad9..15f0be1a43 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -463,14 +463,6 @@ static unsigned long psu_peripherals_init_data(void)
 	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
 	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
-	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
-	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
-	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
-	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
-	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
 	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
 	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
 	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index aac2eb7bc1..8bdc67748e 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -580,8 +580,17 @@ int board_late_init(void)
 		break;
 	case EMMC_MODE:
 		puts("EMMC_MODE\n");
-		mode = "mmc0";
-		env_set("modeboot", "emmcboot");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			puts("Boot from EMMC but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
+
+		mode = "mmc";
+		bootseq = dev->seq;
 		break;
 	case SD_MODE:
 		puts("SD_MODE\n");
@@ -658,6 +667,8 @@ int board_late_init(void)
 	initrd_hi = round_down(initrd_hi, SZ_16M);
 	env_set_addr("initrd_high", (void *)initrd_hi);
 
+	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
 	reset_reason();
 
 	return 0;
diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index df29274207..702367b2a2 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -18,20 +18,7 @@
 static struct bl2_to_bl31_params_mem bl31_params_mem;
 static struct bl31_params *bl2_to_bl31_params;
 
-/**
- * bl2_plat_get_bl31_params() - prepare params for bl31.
- *
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- *
- * @return bl31 params structure pointer
- */
-static struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
+__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
 						    uintptr_t bl33_entry,
 						    uintptr_t fdt_addr)
 {
@@ -112,7 +99,7 @@ static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
 
 static int spl_fit_images_find(void *blob, int os)
 {
-	int parent, node, ndepth;
+	int parent, node, ndepth = 0;
 	const void *data;
 
 	if (!blob)
diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig
deleted file mode 100644
index 43aacf322b..0000000000
--- a/configs/avnet_ultra96_rev1_defconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff010000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_BOOTMENU=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_BIND=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-# CONFIG_NETDEVICES is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQ_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_WDT=y
-CONFIG_WDT_CDNS=y
-CONFIG_SPL_GZIP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index 177558db41..71e0d2726e 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -57,5 +56,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 11428e1e03..6488bca2c0 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -9,7 +9,6 @@ CONFIG_FIT_VERBOSE=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_BOOTDELAY=5
 CONFIG_SUPPORT_RAW_INITRD=y
-# CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig
deleted file mode 100644
index 0e6d8b518a..0000000000
--- a/configs/xilinx_zynqmp_a2197_revA_defconfig
+++ /dev/null
@@ -1,113 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
-CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-g-a2197-00-revA zynqmp-p-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig
deleted file mode 100644
index faf7e45a9a..0000000000
--- a/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-e-a2197-00-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig
deleted file mode 100644
index abef223df8..0000000000
--- a/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-g-a2197-00-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig
deleted file mode 100644
index db5eccc436..0000000000
--- a/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-01-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig
deleted file mode 100644
index 9228ce186e..0000000000
--- a/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-02-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig
deleted file mode 100644
index af2ab307d8..0000000000
--- a/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-03-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index e861cf6910..d953c91a66 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -49,4 +49,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 # CONFIG_DM_WARN is not set
 # CONFIG_DM_DEVICE_REMOVE is not set
 # CONFIG_MMC is not set
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 644223633b..cb2983d247 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 5b468f1cfa..f7bec364c3 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index d490f357b7..01e0971991 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -51,4 +51,5 @@ CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SYS_NAND_MAX_CHIPS=2
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 21aafe1d27..20e76cb11e 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -50,4 +50,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ARASAN=y
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 902dceb0f6..c6e03cd256 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -62,4 +62,5 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
+CONFIG_PANIC_HANG=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
deleted file mode 100644
index ba2cbaba58..0000000000
--- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-p-a2197-00-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index c7e365d009..2327eeee4a 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
@@ -16,10 +17,14 @@ CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTMENU=y
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_BIND=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FPGA_LOADBP=y
@@ -29,15 +34,19 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_BOARD=y
-CONFIG_ENV_IS_IN_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
@@ -53,7 +62,9 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
 CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_I2C_MUX=y
@@ -65,29 +76,41 @@ CONFIG_I2C_EEPROM=y
 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
 CONFIG_SYS_I2C_EEPROM_ADDR=0x0
 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_MAX_CHIPS=2
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHY_MARVELL=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI=y
 CONFIG_PHY_VITESSE=y
+CONFIG_PHY_XILINX_GMII2RGMII=y
 CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_SPI=y
+CONFIG_ZYNQ_SPI=y
 CONFIG_ZYNQMP_GQSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
@@ -101,4 +124,13 @@ CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
 CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
 CONFIG_USB_FUNCTION_THOR=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_GZIP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
deleted file mode 100644
index 73617cedd2..0000000000
--- a/configs/xilinx_zynqmp_zc1232_revA_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
deleted file mode 100644
index 3341af1444..0000000000
--- a/configs/xilinx_zynqmp_zc1254_revA_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
deleted file mode 100644
index 7c10770d28..0000000000
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
deleted file mode 100644
index f05050da98..0000000000
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_DM_MMC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_ARASAN=y
-CONFIG_SYS_NAND_MAX_CHIPS=2
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
deleted file mode 100644
index 9099c582e5..0000000000
--- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff010000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_ARASAN=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
deleted file mode 100644
index 499bf1b278..0000000000
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
deleted file mode 100644
index e1cc924251..0000000000
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
deleted file mode 100644
index d53a0366e5..0000000000
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff010000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_BOOTMENU=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_BIND=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-# CONFIG_NETDEVICES is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQ_SPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_SPL_GZIP=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
deleted file mode 100644
index 04daccfc88..0000000000
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_GPIO_HOG=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
deleted file mode 100644
index c5a3c619ba..0000000000
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_GPIO_HOG=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_SPL_GZIP=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
deleted file mode 100644
index 23341d609d..0000000000
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ /dev/null
@@ -1,110 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_GPIO_HOG=y
-CONFIG_XILINX_GPIO=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
deleted file mode 100644
index 8a81111f4b..0000000000
--- a/configs/xilinx_zynqmp_zcu104_revA_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
deleted file mode 100644
index 7068ad39a9..0000000000
--- a/configs/xilinx_zynqmp_zcu104_revC_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
deleted file mode 100644
index 2878d2d008..0000000000
--- a/configs/xilinx_zynqmp_zcu106_revA_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_THOR_DOWNLOAD=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
-CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
-CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
-CONFIG_USB_FUNCTION_THOR=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig
deleted file mode 100644
index 40cae18ab6..0000000000
--- a/configs/xilinx_zynqmp_zcu111_revA_defconfig
+++ /dev/null
@@ -1,93 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
deleted file mode 100644
index 279fa5d435..0000000000
--- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
deleted file mode 100644
index 0a334260ed..0000000000
--- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-# CONFIG_SPL_FS_FAT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
-CONFIG_DEBUG_UART=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_MISC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_XILINX_GMII2RGMII=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig
deleted file mode 100644
index 48d760a962..0000000000
--- a/configs/xilinx_zynqmp_zcu216_revA_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x8000000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_ZYNQMP_USB=y
-CONFIG_DEBUG_UART=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_ATF=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
-CONFIG_CMD_FPGA_LOADP=y
-CONFIG_CMD_FPGA_LOAD_SECURE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu216-revA"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_CLK_ZYNQMP=y
-CONFIG_DFU_RAM=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_ZYNQMPPL=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_CADENCE=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
-CONFIG_SYS_I2C_EEPROM_ADDR=0x0
-CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SF_DUAL_FLASH=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TI=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_FIXED=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_ZYNQ_GEM=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_DEBUG_UART_ZYNQ=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_ZYNQ_SERIAL=y
-CONFIG_SPI=y
-CONFIG_ZYNQMP_GQSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index dea58b5581..2a2aa2f4f1 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -187,6 +187,5 @@ static const struct udevice_id zynqmp_firmware_ids[] = {
 U_BOOT_DRIVER(zynqmp_firmware) = {
 	.id = UCLASS_FIRMWARE,
 	.name = "zynqmp-firmware",
-	.probe = dm_scan_fdt_dev,
 	.of_match = zynqmp_firmware_ids,
 };
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 16165f8839..5de72fb46c 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -236,6 +236,7 @@ endif
 config NAND_ARASAN
 	bool "Configure Arasan Nand"
 	select SYS_NAND_SELF_INIT
+	select DM_MTD
 	imply CMD_NAND
 	help
 	  This enables Nand driver support for Arasan nand flash
@@ -280,6 +281,7 @@ endif
 config NAND_ZYNQ
 	bool "Support for Zynq Nand controller"
 	select SYS_NAND_SELF_INIT
+	select DM_MTD
 	imply CMD_NAND
 	help
 	  This enables Nand driver support for Nand flash controller
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 2cd3f64dc6..d1b1a4263a 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -15,14 +15,25 @@
 #include <linux/mtd/nand_ecc.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <dm.h>
 #include <nand.h>
 
-struct arasan_nand_info {
-	void __iomem *nand_base;
+struct nand_config {
 	u32 page;
 	bool on_die_ecc_enabled;
 };
 
+struct nand_drv {
+	struct nand_regs *reg;
+	struct nand_config config;
+};
+
+struct arasan_nand_info {
+	struct udevice *dev;
+	struct nand_drv nand_ctrl;
+	struct nand_chip nand_chip;
+};
+
 struct nand_regs {
 	u32 pkt_reg;
 	u32 memadr_reg1;
@@ -54,8 +65,6 @@ struct nand_regs {
 	u32 data_if_reg;
 };
 
-#define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
-
 struct arasan_nand_command_format {
 	u8 cmd1;
 	u8 cmd2;
@@ -259,30 +268,32 @@ static u32 buf_index;
 
 static struct nand_ecclayout nand_oob;
 
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(nand_chip);
 	u32 reg_val;
 
-	reg_val = readl(&arasan_nand_base->memadr_reg2);
+	reg_val = readl(&info->reg->memadr_reg2);
 	if (chip == 0) {
 		reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK;
-		writel(reg_val, &arasan_nand_base->memadr_reg2);
+		writel(reg_val, &info->reg->memadr_reg2);
 	} else if (chip == 1) {
 		reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK;
-		writel(reg_val, &arasan_nand_base->memadr_reg2);
+		writel(reg_val, &info->reg->memadr_reg2);
 	}
 }
 
-static void arasan_nand_enable_ecc(void)
+static void arasan_nand_enable_ecc(struct mtd_info *mtd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val;
 
-	reg_val = readl(&arasan_nand_base->cmd_reg);
+	reg_val = readl(&info->reg->cmd_reg);
 	reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
 
-	writel(reg_val, &arasan_nand_base->cmd_reg);
+	writel(reg_val, &info->reg->cmd_reg);
 }
 
 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
@@ -323,7 +334,8 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct arasan_nand_info *nand = nand_get_controller_data(chip);
+	struct nand_drv *info = nand_get_controller_data(chip);
+	struct nand_config *nand = &info->config;
 	u32 reg_val, i, pktsize, pktnum;
 	u32 *bufptr = (u32 *)buf;
 	u32 timeout;
@@ -340,20 +352,20 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 	else
 		pktnum = size/pktsize;
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
 		   ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
-	writel(reg_val, &arasan_nand_base->intsts_enr);
+	writel(reg_val, &info->reg->intsts_enr);
 
-	reg_val = readl(&arasan_nand_base->pkt_reg);
+	reg_val = readl(&info->reg->pkt_reg);
 	reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 		     ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 	reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
 		    pktsize;
-	writel(reg_val, &arasan_nand_base->pkt_reg);
+	writel(reg_val, &info->reg->pkt_reg);
 
 	if (!nand->on_die_ecc_enabled) {
-		arasan_nand_enable_ecc();
+		arasan_nand_enable_ecc(mtd);
 		addr_cycles = arasan_nand_get_addrcycle(mtd);
 		if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
 			return ERR_ADDR_CYCLE;
@@ -361,13 +373,13 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 		writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
 		       NAND_CMD_RNDOUT | (addr_cycles <<
 		       ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
-		       &arasan_nand_base->ecc_sprcmd_reg);
+		       &info->reg->ecc_sprcmd_reg);
 	}
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
 	while (rdcount < pktnum) {
 		timeout = ARASAN_NAND_POLL_TIMEOUT;
-		while (!(readl(&arasan_nand_base->intsts_reg) &
+		while (!(readl(&info->reg->intsts_reg) &
 			ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
 			udelay(1);
 			timeout--;
@@ -380,20 +392,20 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 		rdcount++;
 
 		if (pktnum == rdcount) {
-			reg_val = readl(&arasan_nand_base->intsts_enr);
+			reg_val = readl(&info->reg->intsts_enr);
 			reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
-			writel(reg_val, &arasan_nand_base->intsts_enr);
+			writel(reg_val, &info->reg->intsts_enr);
 		} else {
-			reg_val = readl(&arasan_nand_base->intsts_enr);
+			reg_val = readl(&info->reg->intsts_enr);
 			writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-			       &arasan_nand_base->intsts_enr);
+			       &info->reg->intsts_enr);
 		}
-		reg_val = readl(&arasan_nand_base->intsts_reg);
+		reg_val = readl(&info->reg->intsts_reg);
 		writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-		       &arasan_nand_base->intsts_reg);
+		       &info->reg->intsts_reg);
 
 		for (i = 0; i < pktsize/4; i++)
-			bufptr[i] = readl(&arasan_nand_base->buf_dataport);
+			bufptr[i] = readl(&info->reg->buf_dataport);
 
 
 		bufptr += pktsize/4;
@@ -402,12 +414,12 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 			break;
 
 		writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-		       &arasan_nand_base->intsts_enr);
+		       &info->reg->intsts_enr);
 	}
 
 	timeout = ARASAN_NAND_POLL_TIMEOUT;
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -417,21 +429,21 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 		return -ETIMEDOUT;
 	}
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	if (!nand->on_die_ecc_enabled) {
-		if (readl(&arasan_nand_base->intsts_reg) &
+		if (readl(&info->reg->intsts_reg) &
 		    ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
 			printf("arasan rd_page:sbiterror\n");
 			return -1;
 		}
 
-		if (readl(&arasan_nand_base->intsts_reg) &
+		if (readl(&info->reg->intsts_reg) &
 		    ARASAN_NAND_INT_STS_ERR_EN_MASK) {
 			mtd->ecc_stats.failed++;
 			printf("arasan rd_page:multibiterror\n");
@@ -455,9 +467,11 @@ static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
 	return status;
 }
 
-static void arasan_nand_fill_tx(const u8 *buf, int len)
+static void arasan_nand_fill_tx(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	u32 __iomem *nand = &arasan_nand_base->buf_dataport;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
+	u32 __iomem *nand = &info->reg->buf_dataport;
 
 	if (((unsigned long)buf & 0x3) != 0) {
 		if (((unsigned long)buf & 0x1) != 0) {
@@ -499,13 +513,14 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, const u8 *buf, int oob_required,
 		int page)
 {
+	struct nand_drv *info = nand_get_controller_data(chip);
+	struct nand_config *nand = &info->config;
 	u32 reg_val, i, pktsize, pktnum;
 	const u32 *bufptr = (const u32 *)buf;
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 	u32 size = mtd->writesize;
 	u32 rdcount = 0;
 	u8 column_addr_cycles;
-	struct arasan_nand_info *nand = nand_get_controller_data(chip);
 
 	if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
 		pktsize = ARASAN_NAND_PKTSIZE_1K;
@@ -517,25 +532,25 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 	else
 		pktnum = size/pktsize;
 
-	reg_val = readl(&arasan_nand_base->pkt_reg);
+	reg_val = readl(&info->reg->pkt_reg);
 	reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 		     ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 	reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
-	writel(reg_val, &arasan_nand_base->pkt_reg);
+	writel(reg_val, &info->reg->pkt_reg);
 
 	if (!nand->on_die_ecc_enabled) {
-		arasan_nand_enable_ecc();
+		arasan_nand_enable_ecc(mtd);
 		column_addr_cycles = (chip->onfi_params.addr_cycles &
 				      ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
 				      ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
 		writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
-		       &arasan_nand_base->ecc_sprcmd_reg);
+		       &info->reg->ecc_sprcmd_reg);
 	}
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
 	while (rdcount < pktnum) {
 		timeout = ARASAN_NAND_POLL_TIMEOUT;
-		while (!(readl(&arasan_nand_base->intsts_reg) &
+		while (!(readl(&info->reg->intsts_reg) &
 			ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
 			udelay(1);
 			timeout--;
@@ -549,21 +564,21 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 		rdcount++;
 
 		if (pktnum == rdcount) {
-			reg_val = readl(&arasan_nand_base->intsts_enr);
+			reg_val = readl(&info->reg->intsts_enr);
 			reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
-			writel(reg_val, &arasan_nand_base->intsts_enr);
+			writel(reg_val, &info->reg->intsts_enr);
 		} else {
-			reg_val = readl(&arasan_nand_base->intsts_enr);
+			reg_val = readl(&info->reg->intsts_enr);
 			writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-			       &arasan_nand_base->intsts_enr);
+			       &info->reg->intsts_enr);
 		}
 
-		reg_val = readl(&arasan_nand_base->intsts_reg);
+		reg_val = readl(&info->reg->intsts_reg);
 		writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-		       &arasan_nand_base->intsts_reg);
+		       &info->reg->intsts_reg);
 
 		for (i = 0; i < pktsize/4; i++)
-			writel(bufptr[i], &arasan_nand_base->buf_dataport);
+			writel(bufptr[i], &info->reg->buf_dataport);
 
 		bufptr += pktsize/4;
 
@@ -571,12 +586,12 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 			break;
 
 		writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-		       &arasan_nand_base->intsts_enr);
+		       &info->reg->intsts_enr);
 	}
 
 	timeout = ARASAN_NAND_POLL_TIMEOUT;
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -586,12 +601,12 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 		return -ETIMEDOUT;
 	}
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	if (oob_required)
 		chip->ecc.write_oob(mtd, chip, nand->page);
@@ -620,22 +635,25 @@ static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 	return status;
 }
 
-static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
+static int arasan_nand_reset(struct mtd_info *mtd,
+			     struct arasan_nand_command_format *curr_cmd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 	u32 cmd_reg = 0;
 
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	cmd_reg = readl(&arasan_nand_base->cmd_reg);
+	       &info->reg->intsts_enr);
+	cmd_reg = readl(&info->reg->cmd_reg);
 	cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
 
 	cmd_reg |= curr_cmd->cmd1 |
 		  (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
-	writel(cmd_reg, &arasan_nand_base->cmd_reg);
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(cmd_reg, &info->reg->cmd_reg);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -646,10 +664,10 @@ static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
 	}
 
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
+	       &info->reg->intsts_enr);
 
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	return 0;
 }
@@ -688,12 +706,14 @@ static u8 arasan_nand_page(struct mtd_info *mtd)
 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
 			int column, int page_addr, struct mtd_info *mtd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val, page;
 	u8 page_val, addr_cycles;
 
 	writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->cmd_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->cmd_reg);
 	reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 	reg_val |= curr_cmd->cmd1 |
 		   (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
@@ -711,7 +731,7 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
 
 	reg_val |= (addr_cycles <<
 		   ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
-	writel(reg_val, &arasan_nand_base->cmd_reg);
+	writel(reg_val, &info->reg->cmd_reg);
 
 	if (page_addr == -1)
 		page_addr = 0;
@@ -719,30 +739,32 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
 	page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 		ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
 	column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
-	writel(page|column, &arasan_nand_base->memadr_reg1);
+	writel(page | column, &info->reg->memadr_reg1);
 
-	reg_val = readl(&arasan_nand_base->memadr_reg2);
+	reg_val = readl(&info->reg->memadr_reg2);
 	reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 	reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
-	writel(reg_val, &arasan_nand_base->memadr_reg2);
+	writel(reg_val, &info->reg->memadr_reg2);
 
 	return 0;
 }
 
 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val;
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 
-	reg_val = readl(&arasan_nand_base->pkt_reg);
+	reg_val = readl(&info->reg->pkt_reg);
 	reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 		     ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 
 	reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
-	writel(reg_val, &arasan_nand_base->pkt_reg);
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(reg_val, &info->reg->pkt_reg);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -751,19 +773,19 @@ static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 	if (!timeout)
 		puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
-	writel(reg_val, &arasan_nand_base->intsts_enr);
+	writel(reg_val, &info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
-	arasan_nand_fill_tx(buf, len);
+	arasan_nand_fill_tx(mtd, buf, len);
 
 	timeout = ARASAN_NAND_POLL_TIMEOUT;
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -771,24 +793,26 @@ static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 	if (!timeout)
 		puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
 
-	writel(readl(&arasan_nand_base->intsts_enr) |
+	writel(readl(&info->reg->intsts_enr) |
 	       ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	writel(readl(&arasan_nand_base->intsts_reg) |
+	       &info->reg->intsts_enr);
+	writel(readl(&info->reg->intsts_reg) |
 	       ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 }
 
 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 			      int column, int page_addr, struct mtd_info *mtd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val, page;
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 	u8 row_addr_cycles;
 
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->cmd_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->cmd_reg);
 	reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 	reg_val |= curr_cmd->cmd1 |
 		   (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
@@ -801,21 +825,21 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 	reg_val |= (row_addr_cycles <<
 		    ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
 
-	writel(reg_val, &arasan_nand_base->cmd_reg);
+	writel(reg_val, &info->reg->cmd_reg);
 
 	page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 		ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
 	writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
-	       &arasan_nand_base->memadr_reg1);
+	       &info->reg->memadr_reg1);
 
-	reg_val = readl(&arasan_nand_base->memadr_reg2);
+	reg_val = readl(&info->reg->memadr_reg2);
 	reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 	reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
-	writel(reg_val, &arasan_nand_base->memadr_reg2);
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(reg_val, &info->reg->memadr_reg2);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -825,12 +849,12 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 		return -ETIMEDOUT;
 	}
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	return 0;
 }
@@ -838,13 +862,15 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
 				int column, int page_addr, struct mtd_info *mtd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val;
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 	u8 addr_cycles;
 
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->cmd_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->cmd_reg);
 	reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 	reg_val |= curr_cmd->cmd1 |
 		   (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
@@ -857,16 +883,16 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
 	reg_val |= (addr_cycles <<
 		    ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
 
-	writel(reg_val, &arasan_nand_base->cmd_reg);
+	writel(reg_val, &info->reg->cmd_reg);
 
-	reg_val = readl(&arasan_nand_base->pkt_reg);
+	reg_val = readl(&info->reg->pkt_reg);
 	reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 		     ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 	reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
-	writel(reg_val, &arasan_nand_base->pkt_reg);
+	writel(reg_val, &info->reg->pkt_reg);
 
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -877,12 +903,12 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
 		return -ETIMEDOUT;
 	}
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	return 0;
 }
@@ -890,14 +916,16 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
 			       int column, int page_addr, struct mtd_info *mtd)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val, addr_cycles, page;
 	u8 page_val;
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-	       &arasan_nand_base->intsts_enr);
+	       &info->reg->intsts_enr);
 
-	reg_val = readl(&arasan_nand_base->cmd_reg);
+	reg_val = readl(&info->reg->cmd_reg);
 	reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
 	reg_val |= curr_cmd->cmd1 |
 		   (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
@@ -919,7 +947,7 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
 		return ERR_ADDR_CYCLE;
 
 	reg_val |= (addr_cycles << 28);
-	writel(reg_val, &arasan_nand_base->cmd_reg);
+	writel(reg_val, &info->reg->cmd_reg);
 
 	if (page_addr == -1)
 		page_addr = 0;
@@ -927,12 +955,12 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
 	page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
 		ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
 	column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
-	writel(page | column, &arasan_nand_base->memadr_reg1);
+	writel(page | column, &info->reg->memadr_reg1);
 
-	reg_val = readl(&arasan_nand_base->memadr_reg2);
+	reg_val = readl(&info->reg->memadr_reg2);
 	reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
 	reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
-	writel(reg_val, &arasan_nand_base->memadr_reg2);
+	writel(reg_val, &info->reg->memadr_reg2);
 
 	buf_index = 0;
 
@@ -941,19 +969,21 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
 
 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 {
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 reg_val, i;
 	u32 *bufptr = (u32 *)buf;
 	u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
 
-	reg_val = readl(&arasan_nand_base->pkt_reg);
+	reg_val = readl(&info->reg->pkt_reg);
 	reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
 		     ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
 	reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
-	writel(reg_val, &arasan_nand_base->pkt_reg);
+	writel(reg_val, &info->reg->pkt_reg);
 
-	writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
+	writel(curr_cmd->pgm, &info->reg->pgm_reg);
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -962,26 +992,26 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 	if (!timeout)
 		puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
-	writel(reg_val, &arasan_nand_base->intsts_enr);
+	writel(reg_val, &info->reg->intsts_enr);
 
 	writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 
 	buf_index = 0;
 	for (i = 0; i < size / 4; i++)
-		bufptr[i] = readl(&arasan_nand_base->buf_dataport);
+		bufptr[i] = readl(&info->reg->buf_dataport);
 
 	if (size & 0x03)
-		bufptr[i] = readl(&arasan_nand_base->buf_dataport);
+		bufptr[i] = readl(&info->reg->buf_dataport);
 
 	timeout = ARASAN_NAND_POLL_TIMEOUT;
 
-	while (!(readl(&arasan_nand_base->intsts_reg) &
+	while (!(readl(&info->reg->intsts_reg) &
 		ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
 		udelay(1);
 		timeout--;
@@ -990,17 +1020,18 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 	if (!timeout)
 		puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
 
-	reg_val = readl(&arasan_nand_base->intsts_enr);
+	reg_val = readl(&info->reg->intsts_enr);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
-	reg_val = readl(&arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_enr);
+	reg_val = readl(&info->reg->intsts_reg);
 	writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_reg);
+	       &info->reg->intsts_reg);
 }
 
 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(chip);
 	u32 size;
 	u8 val;
 	struct nand_onfi_params *p;
@@ -1016,7 +1047,7 @@ static u8 arasan_nand_read_byte(struct mtd_info *mtd)
 		else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
 			size = 4;
 		else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
-			return readb(&arasan_nand_base->flash_sts_reg);
+			return readb(&info->reg->flash_sts_reg);
 		else
 			size = 8;
 		chip->read_buf(mtd, &buf_data[0], size);
@@ -1031,13 +1062,14 @@ static u8 arasan_nand_read_byte(struct mtd_info *mtd)
 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 				     int column, int page_addr)
 {
-	u32 i, ret = 0;
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct arasan_nand_info *nand = nand_get_controller_data(chip);
+	struct nand_drv *info = nand_get_controller_data(chip);
+	struct nand_config *nand = &info->config;
+	u32 i, ret = 0;
 
 	curr_cmd = NULL;
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
-	       &arasan_nand_base->intsts_enr);
+	       &info->reg->intsts_enr);
 
 	if ((command == NAND_CMD_READOOB) &&
 	    (mtd->writesize > 512)) {
@@ -1060,7 +1092,7 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 	}
 
 	if (curr_cmd->cmd1 == NAND_CMD_RESET)
-		ret = arasan_nand_reset(curr_cmd);
+		ret = arasan_nand_reset(mtd, curr_cmd);
 
 	if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
 	    (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
@@ -1088,7 +1120,7 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 static void arasan_check_ondie(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
-	struct arasan_nand_info *nand = nand_get_controller_data(nand_chip);
+	struct nand_config *nand = nand_get_controller_data(nand_chip);
 	u8 maf_id, dev_id;
 	u8 get_feature[4];
 	u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
@@ -1131,9 +1163,10 @@ static void arasan_check_ondie(struct mtd_info *mtd)
 
 static int arasan_nand_ecc_init(struct mtd_info *mtd)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *info = nand_get_controller_data(nand_chip);
 	int found = -1;
 	u32 regval, eccpos_start, i, eccaddr;
-	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 
 	for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
 		if ((ecc_matrix[i].pagesize == mtd->writesize) &&
@@ -1157,14 +1190,14 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	regval = eccaddr |
 		 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
 		 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
-	writel(regval, &arasan_nand_base->ecc_reg);
+	writel(regval, &info->reg->ecc_reg);
 
 	if (ecc_matrix[found].bch) {
-		regval = readl(&arasan_nand_base->memadr_reg2);
+		regval = readl(&info->reg->memadr_reg2);
 		regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
 		regval |= (ecc_matrix[found].bchval <<
 			   ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
-		writel(regval, &arasan_nand_base->memadr_reg2);
+		writel(regval, &info->reg->memadr_reg2);
 	}
 
 	nand_oob.eccbytes = ecc_matrix[found].eccsize;
@@ -1184,21 +1217,18 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	return 0;
 }
 
-static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
+static int arasan_probe(struct udevice *dev)
 {
-	struct arasan_nand_info *nand;
+	struct arasan_nand_info *arasan = dev_get_priv(dev);
+	struct nand_chip *nand_chip = &arasan->nand_chip;
+	struct nand_drv *info = &arasan->nand_ctrl;
+	struct nand_config *nand = &info->config;
 	struct mtd_info *mtd;
 	int err = -1;
 
-	nand = calloc(1, sizeof(struct arasan_nand_info));
-	if (!nand) {
-		printf("%s: failed to allocate\n", __func__);
-		return err;
-	}
-
-	nand->nand_base = arasan_nand_base;
+	info->reg = (struct nand_regs *)dev_read_addr(dev);
 	mtd = nand_to_mtd(nand_chip);
-	nand_set_controller_data(nand_chip, nand);
+	nand_set_controller_data(nand_chip, &arasan->nand_ctrl);
 
 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
 	nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
@@ -1214,8 +1244,8 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 	nand_chip->write_buf = arasan_nand_write_buf;
 	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
 
-	writel(0x0, &arasan_nand_base->cmd_reg);
-	writel(0x0, &arasan_nand_base->pgm_reg);
+	writel(0x0, &info->reg->cmd_reg);
+	writel(0x0, &info->reg->pgm_reg);
 
 	/* first scan to find the device and get the page size */
 	if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) {
@@ -1253,7 +1283,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 		goto fail;
 	}
 
-	if (nand_register(devnum, mtd)) {
+	if (nand_register(0, mtd)) {
 		printf("Nand Register Fail\n");
 		goto fail;
 	}
@@ -1264,10 +1294,26 @@ fail:
 	return err;
 }
 
+static const struct udevice_id arasan_nand_dt_ids[] = {
+	{.compatible = "arasan,nfc-v3p10",},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(arasan_nand) = {
+	.name = "arasan-nand",
+	.id = UCLASS_MTD,
+	.of_match = arasan_nand_dt_ids,
+	.probe = arasan_probe,
+	.priv_auto_alloc_size = sizeof(struct arasan_nand_info),
+};
+
 void board_nand_init(void)
 {
-	struct nand_chip *nand = &nand_chip[0];
+	struct udevice *dev;
+	int ret;
 
-	if (arasan_nand_init(nand, 0))
-		puts("NAND init failed\n");
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_GET_DRIVER(arasan_nand), &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
 }
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index e932a58bf6..28db4153f5 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -11,12 +11,14 @@
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <nand.h>
+#include <linux/ioport.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand_ecc.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <dm.h>
 
 /* The NAND flash driver defines */
 #define ZYNQ_NAND_CMD_PHASE		1
@@ -120,22 +122,31 @@ struct zynq_nand_smc_regs {
 	u32 reserved2[2];
 	u32 eval0r;		/* 0x418 */
 };
-#define zynq_nand_smc_base	((struct zynq_nand_smc_regs __iomem *)\
-				ZYNQ_SMC_BASEADDR)
 
 /*
- * struct zynq_nand_info - Defines the NAND flash driver instance
+ * struct nand_config - Defines the NAND flash driver instance
  * @parts:		Pointer to the mtd_partition structure
  * @nand_base:		Virtual address of the NAND flash device
  * @end_cmd_pending:	End command is pending
  * @end_cmd:		End command
  */
-struct zynq_nand_info {
+struct nand_config {
 	void __iomem	*nand_base;
 	u8		end_cmd_pending;
 	u8		end_cmd;
 };
 
+struct nand_drv {
+	struct zynq_nand_smc_regs *reg;
+	struct nand_config config;
+};
+
+struct zynq_nand_info {
+	struct udevice *dev;
+	struct nand_drv nand_ctrl;
+	struct nand_chip nand_chip;
+};
+
 /*
  * struct zynq_nand_command_format - Defines NAND flash command format
  * @start_cmd:		First cycle command (Start command)
@@ -239,16 +250,18 @@ static struct nand_bbt_descr bbt_mirror_descr = {
  *
  * returns: status for command completion, -1 for Timeout
  */
-static int zynq_nand_waitfor_ecc_completion(void)
+static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *smc = nand_get_controller_data(nand_chip);
 	unsigned long timeout;
 	u32 status;
 
 	/* Wait max 10us */
 	timeout = 10;
-	status = readl(&zynq_nand_smc_base->esr);
+	status = readl(&smc->reg->esr);
 	while (status & ZYNQ_NAND_ECC_BUSY) {
-		status = readl(&zynq_nand_smc_base->esr);
+		status = readl(&smc->reg->esr);
 		if (timeout == 0)
 			return -1;
 		timeout--;
@@ -266,33 +279,35 @@ static int zynq_nand_waitfor_ecc_completion(void)
  *
  * returns:	0 on success or error value on failure
  */
-static int zynq_nand_init_nand_flash(int option)
+static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *smc = nand_get_controller_data(nand_chip);
 	u32 status;
 
 	/* disable interrupts */
-	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+	writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 	/* Initialize the NAND interface by setting cycles and operation mode */
-	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+	writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
 #endif
 	if (option & NAND_BUSWIDTH_16)
-		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
+		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor);
 	else
-		writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
+		writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor);
 
-	writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
+	writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr);
 
 	/* Wait till the ECC operation is complete */
-	status = zynq_nand_waitfor_ecc_completion();
+	status = zynq_nand_waitfor_ecc_completion(mtd);
 	if (status < 0) {
 		printf("%s: Timeout\n", __func__);
 		return status;
 	}
 
 	/* Set the command1 and command2 register */
-	writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
-	writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
+	writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r);
+	writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r);
 
 	return 0;
 }
@@ -311,12 +326,14 @@ static int zynq_nand_init_nand_flash(int option)
 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 		u8 *ecc_code)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *smc = nand_get_controller_data(nand_chip);
 	u32 ecc_value = 0;
 	u8 ecc_reg, ecc_byte;
 	u32 ecc_status;
 
 	/* Wait till the ECC operation is complete */
-	ecc_status = zynq_nand_waitfor_ecc_completion();
+	ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
 	if (ecc_status < 0) {
 		printf("%s: Timeout\n", __func__);
 		return ecc_status;
@@ -324,7 +341,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 
 	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 		/* Read ECC value for each block */
-		ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
+		ecc_value = readl(&smc->reg->eval0r + ecc_reg);
 
 		/* Get the ecc status from ecc read value */
 		ecc_status = (ecc_value >> 24) & 0xFF;
@@ -779,10 +796,11 @@ static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 				 int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *smc = nand_get_controller_data(chip);
 	const struct zynq_nand_command_format *curr_cmd = NULL;
 	u8 addr_cycles = 0;
-	struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
+	struct nand_config *xnand = &smc->config;
 	void *cmd_addr;
 	unsigned long cmd_data = 0;
 	unsigned long cmd_phase_addr = 0;
@@ -821,7 +839,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 	curr_cmd = &zynq_nand_commands[index];
 
 	/* Clear interrupt */
-	writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
+	writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr);
 
 	/* Get the command phase address */
 	if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
@@ -918,7 +936,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  */
 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* Make sure that buf is 32 bit aligned */
 	if (((unsigned long)buf & 0x3) != 0) {
@@ -966,7 +984,7 @@ static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  */
 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	const u32 *nand = chip->IO_ADDR_W;
 
 	/* Make sure that buf is 32 bit aligned */
@@ -1016,13 +1034,15 @@ static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  */
 static int zynq_nand_device_ready(struct mtd_info *mtd)
 {
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct nand_drv *smc = nand_get_controller_data(nand_chip);
 	u32 csr_val;
 
-	csr_val = readl(&zynq_nand_smc_base->csr);
+	csr_val = readl(&smc->reg->csr);
 	/* Check the raw_int_status1 bit */
 	if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
 		/* Clear the interrupt condition */
-		writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
+		writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr);
 		return 1;
 	}
 
@@ -1046,10 +1066,15 @@ static int zynq_nand_check_is_16bit_bw_flash(void)
 	return is_16bit_bw;
 }
 
-static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+static int zynq_nand_probe(struct udevice *dev)
 {
-	struct zynq_nand_info *xnand;
+	struct zynq_nand_info *zynq = dev_get_priv(dev);
+	struct nand_chip *nand_chip = &zynq->nand_chip;
+	struct nand_drv *smc = &zynq->nand_ctrl;
+	struct nand_config *xnand = &smc->config;
 	struct mtd_info *mtd;
+	struct resource res;
+	ofnode of_nand;
 	unsigned long ecc_page_size;
 	u8 maf_id, dev_id, i;
 	u8 get_feature[4];
@@ -1059,17 +1084,20 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 	int err = -1;
 	int is_16bit_bw;
 
-	xnand = calloc(1, sizeof(struct zynq_nand_info));
-	if (!xnand) {
-		printf("%s: failed to allocate\n", __func__);
+	smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
+	of_nand = dev_read_subnode(dev, "flash@e1000000");
+	if (!ofnode_valid(of_nand)) {
+		printf("Failed to find nand node in dt\n");
+		goto fail;
+	}
+	if (ofnode_read_resource(of_nand, 0, &res)) {
+		printf("Failed to get nand resource\n");
 		goto fail;
 	}
 
-	xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
+	xnand->nand_base = (void __iomem *)res.start;
 	mtd = nand_to_mtd(nand_chip);
-
-	nand_chip->priv = xnand;
-	mtd->priv = nand_chip;
+	nand_set_controller_data(nand_chip, &zynq->nand_ctrl);
 
 	/* Set address of NAND IO lines */
 	nand_chip->IO_ADDR_R = xnand->nand_base;
@@ -1100,7 +1128,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
 
 	/* Initialize the NAND flash interface on NAND controller */
-	if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
+	if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) {
 		printf("%s: nand flash init failed\n", __func__);
 		goto fail;
 	}
@@ -1148,9 +1176,9 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 
 	if (ondie_ecc_enabled) {
 		/* Bypass the controller ECC block */
-		ecc_cfg = readl(&zynq_nand_smc_base->emcr);
+		ecc_cfg = readl(&smc->reg->emcr);
 		ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
-		writel(ecc_cfg, &zynq_nand_smc_base->emcr);
+		writel(ecc_cfg, &smc->reg->emcr);
 
 		/* The software ECC routines won't work
 		 * with the SMC controller
@@ -1198,19 +1226,19 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 			ecc_page_size = 0x1;
 			/* Set the ECC memory config register */
 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
-			       &zynq_nand_smc_base->emcr);
+			       &smc->reg->emcr);
 			break;
 		case 1024:
 			ecc_page_size = 0x2;
 			/* Set the ECC memory config register */
 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
-			       &zynq_nand_smc_base->emcr);
+			       &smc->reg->emcr);
 			break;
 		case 2048:
 			ecc_page_size = 0x3;
 			/* Set the ECC memory config register */
 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
-			       &zynq_nand_smc_base->emcr);
+			       &smc->reg->emcr);
 			break;
 		default:
 			nand_chip->ecc.mode = NAND_ECC_SOFT;
@@ -1235,7 +1263,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 		printf("%s: nand_scan_tail failed\n", __func__);
 		goto fail;
 	}
-	if (nand_register(devnum, mtd))
+	if (nand_register(0, mtd))
 		goto fail;
 	return 0;
 fail:
@@ -1243,12 +1271,26 @@ fail:
 	return err;
 }
 
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+static const struct udevice_id zynq_nand_dt_ids[] = {
+	{.compatible = "arm,pl353-smc-r2p1",},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(zynq_nand) = {
+	.name = "zynq-nand",
+	.id = UCLASS_MTD,
+	.of_match = zynq_nand_dt_ids,
+	.probe = zynq_nand_probe,
+	.priv_auto_alloc_size = sizeof(struct zynq_nand_info),
+};
 
 void board_nand_init(void)
 {
-	struct nand_chip *nand = &nand_chip[0];
+	struct udevice *dev;
+	int ret;
 
-	if (zynq_nand_init(nand, 0))
-		puts("ZYNQ NAND init failed\n");
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_GET_DRIVER(zynq_nand), &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
 }
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 78f94148b4..c3fe8e3c56 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -173,6 +173,7 @@ struct emac_bd {
 #endif
 };
 
+/* Reduce amount of BUFs if you have limited amount of memory */
 #define RX_BUF 32
 /* Page table entries are set to 1MB, or multiples of 1MB
  * (not < 1MB). driver uses less bd's so use 1MB bdspace.
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index af910e9efc..0ca108ee3d 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -170,21 +170,25 @@ static int spi_post_probe(struct udevice *bus)
 #endif
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	struct dm_spi_ops *ops = spi_get_ops(bus);
-
-	if (ops->claim_bus)
-		ops->claim_bus += gd->reloc_off;
-	if (ops->release_bus)
-		ops->release_bus += gd->reloc_off;
-	if (ops->set_wordlen)
-		ops->set_wordlen += gd->reloc_off;
-	if (ops->xfer)
-		ops->xfer += gd->reloc_off;
-	if (ops->set_speed)
-		ops->set_speed += gd->reloc_off;
-	if (ops->set_mode)
-		ops->set_mode += gd->reloc_off;
-	if (ops->cs_info)
-		ops->cs_info += gd->reloc_off;
+	static int reloc_done;
+
+	if (!reloc_done) {
+		if (ops->claim_bus)
+			ops->claim_bus += gd->reloc_off;
+		if (ops->release_bus)
+			ops->release_bus += gd->reloc_off;
+		if (ops->set_wordlen)
+			ops->set_wordlen += gd->reloc_off;
+		if (ops->xfer)
+			ops->xfer += gd->reloc_off;
+		if (ops->set_speed)
+			ops->set_speed += gd->reloc_off;
+		if (ops->set_mode)
+			ops->set_mode += gd->reloc_off;
+		if (ops->cs_info)
+			ops->cs_info += gd->reloc_off;
+		reloc_done++;
+	}
 #endif
 
 	return 0;
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index f426127edc..dec5001b5f 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -92,7 +92,6 @@
 	"kernel_size_r=0x10000000\0" \
 	"scriptaddr=0x20000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
-	"script_offset_f=0x7F80000\0" \
 	"script_size_f=0x80000\0"
 
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ee1ceebf12..010738363d 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -94,7 +94,6 @@
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-#define CONFIG_PANIC_HANG
 #define CONFIG_SYS_MAXARGS		64
 
 /* Ethernet driver */
@@ -114,7 +113,6 @@
 	"kernel_addr_r=0x18000000\0" \
 	"scriptaddr=0x20000000\0" \
 	"ramdisk_addr_r=0x02100000\0" \
-	"script_offset_f=0x3e80000\0" \
 	"script_size_f=0x80000\0" \
 
 #if defined(CONFIG_MMC_SDHCI_ZYNQ)
@@ -243,7 +241,11 @@
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
 # define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# if defined(CONFIG_SPL_LOAD_FIT)
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.itb"
+# else
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# endif
 #endif
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 189ca81bbe..2d53237df4 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -176,7 +176,16 @@
 #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \
 	"nor "
 
+#define BOOT_TARGET_DEVICES_JTAG(func)  func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+	"jtag "
+
 #define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_JTAG(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_QSPI(func) \
 	BOOT_TARGET_DEVICES_NAND(func) \
@@ -194,7 +203,6 @@
 	"fdt_high=0x20000000\0"		\
 	"initrd_high=0x20000000\0"	\
 	"scriptaddr=0x20000\0"	\
-	"script_offset_f=0xFC0000\0"	\
 	"script_size_f=0x40000\0"	\
 	"fdt_addr_r=0x1f00000\0"        \
 	"pxefile_addr_r=0x2000000\0"    \
diff --git a/include/spl.h b/include/spl.h
index 02aa1ff85d..cd4669f5aa 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -462,6 +462,26 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image,
 void spl_invoke_atf(struct spl_image_info *spl_image);
 
 /**
+ * bl2_plat_get_bl31_params() - prepare params for bl31.
+ * @bl32_entry	address of BL32 executable (secure)
+ * @bl33_entry	address of BL33 executable (non secure)
+ * @fdt_addr	address of Flat Device Tree
+ *
+ * This function assigns a pointer to the memory that the platform has kept
+ * aside to pass platform specific and trusted firmware related information
+ * to BL31. This memory is allocated by allocating memory to
+ * bl2_to_bl31_params_mem structure which is a superset of all the
+ * structure whose information is passed to BL31
+ * NOTE: This function should be called only once and should be done
+ * before generating params to BL31
+ *
+ * @return bl31 params structure pointer
+ */
+struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
+					     uintptr_t bl33_entry,
+					     uintptr_t fdt_addr);
+
+/**
  * spl_optee_entry - entry function for optee
  *
  * args defind in op-tee project
diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py
index bba8d41d96..d117921a6a 100644
--- a/test/py/tests/test_hush_if_test.py
+++ b/test/py/tests/test_hush_if_test.py
@@ -7,6 +7,10 @@ import os
 import os.path
 import pytest
 
+# TODO: These tests should be converted to a C test.
+# For more information please take a look at the thread
+# https://lists.denx.de/pipermail/u-boot/2019-October/388732.html
+
 pytestmark = pytest.mark.buildconfigspec('hush_parser')
 
 # The list of "if test" conditions to test.
@@ -52,6 +56,33 @@ subtests = (
     ('test 123 -ge 123', True),
     ('test 123 -ge 456', False),
 
+    # Octal tests
+
+    ('test 010 -eq 010', True),
+    ('test 010 -eq 011', False),
+
+    ('test 010 -ne 011', True),
+    ('test 010 -ne 010', False),
+
+    # Hexadecimal tests
+
+    ('test 0x2000000 -gt 0x2000001', False),
+    ('test 0x2000000 -gt 0x2000000', False),
+    ('test 0x2000000 -gt 0x1ffffff', True),
+
+    # Mixed tests
+
+    ('test 010 -eq 10', False),
+    ('test 010 -ne 10', True),
+    ('test 0xa -eq 10', True),
+    ('test 0xa -eq 012', True),
+
+    ('test 2000000 -gt 0x1ffffff', False),
+    ('test 0x2000000 -gt 1ffffff', True),
+    ('test 0x2000000 -lt 1ffffff', False),
+    ('test 0x2000000 -eq 2000000', False),
+    ('test 0x2000000 -ne 2000000', True),
+
     ('test -z ""', True),
     ('test -z "aaa"', False),
author	Tom Rini <trini@konsulko.com>	2020-01-16 09:45:40 -0500
committer	Tom Rini <trini@konsulko.com>	2020-01-16 09:45:40 -0500
commit	92329e2413f444d1edf29bab66aefccfd782e0a7 (patch)
tree	f8d5b354b1f228a5258ba01ca801b8e3a5d31792
parent	f47704d4ae494ebc8a25c95202e548ea32f98955 (diff)
parent	ddb55ff8a66dabe3365735eff9f901bb259c223f (diff)
download	u-boot-92329e2413f444d1edf29bab66aefccfd782e0a7.tar.gz