ppc: Remove MPC8610HPCD board

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

12 files changed, 0 insertions, 1214 deletions

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 0f253051f2..294485794b 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -13,11 +13,6 @@ config TARGET_SBC8641D
 	select ARCH_MPC8641
 	select BOARD_EARLY_INIT_F
 
-config TARGET_MPC8610HPCD
-	bool "Support MPC8610HPCD"
-	select ARCH_MPC8610
-	select BOARD_EARLY_INIT_F
-
 config TARGET_MPC8641HPCN
 	bool "Support MPC8641HPCN"
 	select ARCH_MPC8641
@@ -62,7 +57,6 @@ config SYS_FSL_NUM_LAWS
 		Number of local access windows. This is fixed per SoC.
 		If not sure, do not change.
 
-source "board/freescale/mpc8610hpcd/Kconfig"
 source "board/freescale/mpc8641hpcn/Kconfig"
 source "board/sbc8641d/Kconfig"
 source "board/xes/xpedite517x/Kconfig"
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index 7b1c973520..474ae56d44 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -45,36 +45,6 @@ typedef struct pixis {
 	u8 res2[4];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_TARGET_MPC8610HPCD)
-typedef struct pixis {
-	u8 id;
-	u8 ver;	/* also called arch */
-	u8 pver;
-	u8 csr;
-	u8 rst;
-	u8 pwr;
-	u8 aux;
-	u8 spd;
-	u8 brdcfg0;
-	u8 brdcfg1;
-	u8 res[4];
-	u8 led;
-	u8 serno;
-	u8 vctl;
-	u8 vstat;
-	u8 vcfgen0;
-	u8 vcfgen1;
-	u8 vcore0;
-	u8 res1;
-	u8 vboot;
-	u8 vspeed[2];
-	u8 res2;
-	u8 sclk[3];
-	u8 res3;
-	u8 watch;
-	u8 res4[33];
-} __attribute__ ((packed)) pixis_t;
-
 #elif defined(CONFIG_TARGET_MPC8641HPCN)
 typedef struct pixis {
 	u8 id;
diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig
deleted file mode 100644
index 8f713beaa8..0000000000
--- a/board/freescale/mpc8610hpcd/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8610HPCD
-
-config SYS_BOARD
-	default "mpc8610hpcd"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8610HPCD"
-
-endif
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
deleted file mode 100644
index 9b1e0cd4e5..0000000000
--- a/board/freescale/mpc8610hpcd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8610HPCD BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8610hpcd/
-F:	include/configs/MPC8610HPCD.h
-F:	configs/MPC8610HPCD_defconfig
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
deleted file mode 100644
index 3a02a06416..0000000000
--- a/board/freescale/mpc8610hpcd/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2007 Freescale Semiconductor, Inc.
-
-obj-y	+= mpc8610hpcd.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
-obj-y	+= law.o
-obj-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README
deleted file mode 100644
index 066e625d48..0000000000
--- a/board/freescale/mpc8610hpcd/README
+++ /dev/null
@@ -1,73 +0,0 @@
-Freescale MPC8610HPCD board
-===========================
-
-
-Building U-Boot
----------------
-
-    $ make MPC8610HPCD_config
-    Configuring for MPC8610HPCD board...
-
-    $ make
-
-
-Flashing U-Boot
----------------
-The flash is 128M starting at 0xF800_0000.
-
-The alternate image is at 0xFBF0_0000
-The      boot image is at 0xFFF0_0000.
-
-
-To Flash U-Boot into the booting bank:
-
-	tftp 1000000 u-boot.bin
-	protect off all
-	erase fff00000 +$filesize
-	cp.b 1000000 fff00000 $filesize
-
-
-To Flash U-Boot into the alternate bank
-
-	tftp 1000000 u-boot.bin
-	erase fbf00000 +$filesize
-	cp.b 1000000 fbf00000 $filesize
-
-
-pixis_reset command
--------------------
-A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-
-DIP Switch Settings
--------------------
-To manually switch the flash banks using the DIP switch
-settings, toggle both SW6:1 and SW6:2.
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
deleted file mode 100644
index c4d985347b..0000000000
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
deleted file mode 100644
index 7bf5e6815d..0000000000
--- a/board/freescale/mpc8610hpcd/law.c
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
-#endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
deleted file mode 100644
index 52bf4da98e..0000000000
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ /dev/null
@@ -1,335 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void);
-phys_size_t fixed_sdram(void);
-int mpc8610hpcd_diu_init(void);
-
-
-/* called before any console output */
-int board_early_init_f(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-
-	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 tmp_val, version;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	/*Do not use 8259PIC*/
-	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
-	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
-
-	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
-	version = in_8(pixis_base + PIXIS_PVER);
-	if(version >= 0x07) {
-		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
-		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
-	}
-
-	/* Using this for DIU init before the driver in linux takes over
-	 *  Enable the TFP410 Encoder (I2C address 0x38)
-	 */
-
-	tmp_val = 0xBF;
-	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	tmp_val = 0x10;
-	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	/*
-	 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
-	 * bank and LBMAP=00 is the alternate bank.  However, the pixis
-	 * altbank code can only set bits, not clear them, so we treat 00 as
-	 * the normal bank and 11 as the alternate.
-	 */
-	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
-	case 0:
-		puts("vBank: Standard\n");
-		break;
-	case 0x40:
-		puts("Promjet\n");
-		break;
-	case 0x80:
-		puts("NAND\n");
-		break;
-	case 0xC0:
-		puts("vBank: Alternate\n");
-		break;
-	}
-
-	mcm->abcr |= 0x00010000; /* 0 */
-	mcm->hpmr3 = 0x80000008; /* 4c */
-	mcm->hpmr0 = 0;
-	mcm->hpmr1 = 0;
-	mcm->hpmr2 = 0;
-	mcm->hpmr4 = 0;
-	mcm->hpmr5 = 0;
-
-	return 0;
-}
-
-
-int dram_init(void)
-{
-	phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram();
-#endif
-
-	setup_ddr_bat(dram_size);
-
-	debug(" DDR: ");
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-	uint d_init;
-
-	ddr->cs0_bnds = 0x0000001f;
-	ddr->cs0_config = 0x80010202;
-
-	ddr->timing_cfg_3 = 0x00000000;
-	ddr->timing_cfg_0 = 0x00260802;
-	ddr->timing_cfg_1 = 0x3935d322;
-	ddr->timing_cfg_2 = 0x14904cc8;
-	ddr->sdram_mode = 0x00480432;
-	ddr->sdram_mode_2 = 0x00000000;
-	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
-	ddr->sdram_data_init = 0xDEADBEEF;
-	ddr->sdram_clk_cntl = 0x03800000;
-	ddr->sdram_cfg_2 = 0x04400010;
-
-#if defined(CONFIG_DDR_ECC)
-	ddr->err_int_en = 0x0000000d;
-	ddr->err_disable = 0x00000000;
-	ddr->err_sbe = 0x00010000;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
-
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
-		udelay(1000);
-
-	debug("DDR: memory initialized\n\n");
-	asm("sync; isync");
-	udelay(500);
-#endif
-
-	return 512 * 1024 * 1024;
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				 PCI_ENET0_MEMADDR,
-				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
-	{}
-};
-#endif
-
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	struct fsl_pci_info pci_info;
-	u32 devdisr;
-	int first_free_busno;
-	int pci_agent;
-
-	devdisr = in_be32(&gur->devdisr);
-
-	first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
-	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: connected to PCI slots as %s" \
-			" (base address %lx)\n",
-			pci_agent ? "Agent" : "Host",
-			pci_info.regs);
-#ifndef CONFIG_PCI_PNP
-		pci1_hose.config_table = pci_mpc86xxcts_config_table;
-#endif
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	return 0;
-}
-#endif
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	i = in_8(pixis_base + PIXIS_SPD);
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33333000;
-		break;
-	case 1:
-		val = 39999600;
-		break;
-	case 2:
-		val = 49999500;
-		break;
-	case 3:
-		val = 66666000;
-		break;
-	case 4:
-		val = 83332500;
-		break;
-	case 5:
-		val = 99999000;
-		break;
-	case 6:
-		val = 133332000;
-		break;
-	case 7:
-		val = 166665000;
-		break;
-	}
-
-	return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	out_8(pixis_base + PIXIS_RST, 0);
-
-	while (1)
-		;
-}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
deleted file mode 100644
index 9b96d0d33f..0000000000
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_diu_fb.h>
-#include "../common/pixis.h"
-
-#define PX_BRDCFG0_DLINK	0x10
-#define PX_BRDCFG0_DVISEL	0x08
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
-	unsigned long speed_ccb, temp, pixval;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000/pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	debug("DIU pixval = %lu\n", pixval);
-
-	/* Modify PXCLK in GUTS CLKDVDR */
-	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-	temp = *guts_clkdvdr & 0x2000FFFF;
-	*guts_clkdvdr = temp;				/* turn off clock */
-	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
-	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	const char *name;
-	int gamma_fix = 0;
-	u32 pixel_format = 0x88883316;
-	u8 temp;
-
-	temp = in_8(&pixis->brdcfg0);
-
-	if (strncmp(port, "dlvds", 5) == 0) {
-		/* Dual link LVDS */
-		gamma_fix = 1;
-		temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
-		name = "Dual-Link LVDS";
-	} else if (strncmp(port, "lvds", 4) == 0) {
-		/* Single link LVDS */
-		temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
-		name = "Single-Link LVDS";
-	} else {
-		/* DVI */
-		if (in_8(&pixis->ver) == 1)	/* Board version */
-			pixel_format = 0x88882317;
-		temp |= PX_BRDCFG0_DVISEL;
-		name = "DVI";
-	}
-
-	printf("DIU:   Switching to %s monitor @ %ux%u\n", name, xres, yres);
-	out_8(&pixis->brdcfg0, temp);
-
-	return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
-}
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
deleted file mode 100644
index b9ef566204..0000000000
--- a/configs/MPC8610HPCD_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8610HPCD=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
deleted file mode 100644
index f444be0d86..0000000000
--- a/include/configs/MPC8610HPCD.h
+++ /dev/null
@@ -1,559 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * MPC8610HPCD board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
-
-/* video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR		0xff800000
-#endif
-
-/*
- * virtual address to be used for temporary mappings.  There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA	0xc0000000
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
-#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-#define CONFIG_ALTIVEC		1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E |0x00100000 )
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
-#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
-
-#if 0 /* TODO */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
-#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
-#define CONFIG_SYS_DDR_SBE		0x000f0000
-
-#endif
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
-#define CONFIG_SYS_FLASH_BASE2		0xf8000000
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-
-#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
-
-#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CONFIG_SYS_BR2_PRELIM		0xf0000000
-#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
-#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE	256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_NAME		"ULI"
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#define CONFIG_ULI526X
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI		1
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
-
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR	0xe0000000
-#define PCI_ENET0_MEMADDR	0xe0000000
-#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif	/* CONFIG_PCI */
-
-/*
- * BAT0		2G	Cacheable, non-guarded
- * 0x0000_0000	2G	DDR
- */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
-
-/*
- * BAT1		1G	Cache-inhibited, guarded
- * 0x8000_0000	256M	PCI-1 Memory
- * 0xa000_0000	256M	PCI-Express 1 Memory
- * 0x9000_0000	256M	PCI-Express 2 Memory
- */
-
-#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
-
-/*
- * BAT2		16M	Cache-inhibited, guarded
- * 0xe100_0000	1M	PCI-1 I/O
- */
-
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-
-/*
- * BAT3		4M	Cache-inhibited, guarded
- * 0xe000_0000	4M	CCSR
- */
-
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT \
-				       | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4		32M	Cache-inhibited, guarded
- * 0xe200_0000	1M	PCI-Express 2 I/O
- * 0xe300_0000	1M	PCI-Express 1 I/O
- */
-
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
-
-/*
- * BAT5		128K	Cacheable, non-guarded
- * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
-
-/*
- * BAT6		256M	Cache-inhibited, guarded
- * 0xf000_0000	256M	FLASH
- */
-#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7		4M	Cache-inhibited, guarded
- * 0xe800_0000	4M	PIXIS
- */
-#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_WATCHDOG			/* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_IPADDR		192.168.1.100
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		0x10000000
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
-	"echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
-	"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
-	"pci w.w $b.0 56 ffff\0"	\
- "pci1err=setenv a e0008; run pcierr\0"	\
- "pci1errc=setenv a e0008; run pcierrc\0"
-#else
-#define	PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
-	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0"	\
- "pcie2regs=setenv a e0009; run pciereg\0"	\
- "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
-	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
-	"pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
-	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
-	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
- "pcie1err=setenv a e000a; run pcieerr\0"	\
- "pcie2err=setenv a e0009; run pcieerr\0"	\
- "pcie1errc=setenv a e000a; run pcieerrc\0"	\
- "pcie2errc=setenv a e0009; run pcieerrc\0"
-#else
-#define	PCIE_ENV ""
-#endif
-
-#define DMA_ENV \
- "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
-	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
- "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
-	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
- "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
-	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
- "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
-	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
-#ifdef ENV_DEBUG
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"							\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "				\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"						\
-"ramdiskaddr=0x18000000\0"					\
-"ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
-"fdtaddr=0x17c00000\0"						\
-"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
-"bdev=sda3\0"					\
-"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-"maxcpus=1"	\
-"eoi=mw e00400b0 0\0"						\
-"iack=md e00400a0 1\0"						\
-"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
-	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
-	"md ${a}f00 5\0" \
-"ddr1regs=setenv a e0002; run ddrreg\0" \
-"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
-	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
-	"md ${a}e60 1; md ${a}ef0 1d\0" \
-"guregs=setenv a e00e0; run gureg\0" \
-"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
-"mcmregs=setenv a e0001; run mcmreg\0" \
-"diuregs=md e002c000 1d\0" \
-"dium=mw e002c01c\0" \
-"diuerr=md e002c014 1\0" \
-"pmregs=md e00e1000 2b\0" \
-"lawregs=md e0000c08 4b\0" \
-"lbcregs=md e0005000 36\0" \
-"dma0regs=md e0021100 12\0" \
-"dma1regs=md e0021180 12\0" \
-"dma2regs=md e0021200 12\0" \
-"dma3regs=md e0021280 12\0" \
- PCI_ENV \
- PCIE_ENV \
- DMA_ENV
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=0x18000000\0"				\
-	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
-	"fdtaddr=0x17c00000\0"					\
-	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
-	"bdev=sda3\0"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND					\
- "setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$serverip:$rootpath "				\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw "				\
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $ramdiskaddr $ramdiskfile;"				\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
-	"console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */