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authorMilan Obuch <u-boot@dino.sk>2020-01-19 22:32:19 -0300
committerMichal Simek <michal.simek@xilinx.com>2020-02-28 12:04:10 +0100
commit1bf9e01b8f82c442029607ab953c6a0d099c7d68 (patch)
tree41c6a8cdedd6813728a358223c3cbdcc1364e8be
parent1a4bf17b0298257b35611453e44f53c72a55f8a7 (diff)
downloadu-boot-1bf9e01b8f82c442029607ab953c6a0d099c7d68.tar.gz
arm: zynq: zybo z7: fix SPL uart init bitrate
The board uses 100 MHz clock for UART bitrate generator, but is configured as 50 MHz on defconfig. This produces wrong console output. The first message, "Debug uart enabled" is received as: "������b" Fix the issue by configuring the correct clock for the UART baudrate generator Signed-off-by: Milan Obuch <u-boot@dino.sk> Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--configs/zynq_zybo_z7_defconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 12e1367e97..1dee757062 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -6,7 +6,7 @@ CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xe0001000
-CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y