diff options
| author | Sean Anderson <seanga2@gmail.com> | 2020-06-24 06:41:22 -0400 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:22 +0800 |
| commit | 627718626b05f715da555cc005426ab10f44bb98 (patch) | |
| tree | dfd68984d33bff8338080a6fc7e81ce0fef75b6e | |
| parent | ab24017a19b482d9026d21a2ec03416c5c4a388d (diff) | |
| download | u-boot-627718626b05f715da555cc005426ab10f44bb98.tar.gz | |
riscv: Enable cpu clock if it is present
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | drivers/cpu/riscv_cpu.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 2d44d1c17b..76b0489d2a 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> */ #include <clk.h> @@ -119,6 +120,24 @@ static int riscv_cpu_bind(struct udevice *dev) return 0; } +static int riscv_cpu_probe(struct udevice *dev) +{ + int ret = 0; + struct clk clk; + + /* Get a clock if it exists */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return 0; + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret == -ENOSYS || ret == -ENOTSUPP) + return 0; + else + return ret; +} + static const struct cpu_ops riscv_cpu_ops = { .get_desc = riscv_cpu_get_desc, .get_info = riscv_cpu_get_info, @@ -135,6 +154,7 @@ U_BOOT_DRIVER(riscv_cpu) = { .id = UCLASS_CPU, .of_match = riscv_cpu_ids, .bind = riscv_cpu_bind, + .probe = riscv_cpu_probe, .ops = &riscv_cpu_ops, .flags = DM_FLAG_PRE_RELOC, }; |