Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.07
----------------

- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914

81 files changed, 5731 insertions, 323 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c57a6460c6..559d3ab6a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -736,6 +736,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-verdin.dtb \
 	imx8mn-ddr4-evk.dtb \
 	imx8mq-evk.dtb \
+	imx8mq-phanbell.dtb \
 	imx8mp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 3502602fbb..b5c12105a9 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
  * Copyright 2019 NXP
  */
 
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
 &{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
@@ -117,3 +125,7 @@
 &fec1 {
 	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
+
+&wdog1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index e60b9faee4..fe6bb9bf03 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -3,6 +3,14 @@
  * Copyright 2020 Toradex
  */
 
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
 &aips1 {
 	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;
@@ -105,3 +113,7 @@
 &usdhc3 {
 	u-boot,dm-spl;
 };
+
+&wdog1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 8aafad2449..1e5e11592f 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -12,7 +12,6 @@
 #include "imx8mm-pinfunc.h"
 
 / {
-	compatible = "fsl,imx8mm";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -141,11 +140,6 @@
 		};
 	};
 
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0 0x80000000>;
-	};
-
 	osc_32k: clock-osc-32k {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -233,7 +227,7 @@
 		ranges = <0x0 0x0 0x0 0x3e000000>;
 
 		aips1: bus@30000000 {
-			compatible = "fsl,aips-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30000000 0x30000000 0x400000>;
@@ -394,7 +388,7 @@
 			};
 
 			sdma2: dma-controller@302c0000 {
-				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 				reg = <0x302c0000 0x10000>;
 				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
@@ -405,7 +399,7 @@
 			};
 
 			sdma3: dma-controller@302b0000 {
-				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 				reg = <0x302b0000 0x10000>;
 				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
@@ -439,7 +433,7 @@
 			};
 
 			anatop: anatop@30360000 {
-				compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
+				compatible = "fsl,imx8mm-anatop", "syscon";
 				reg = <0x30360000 0x10000>;
 			};
 
@@ -479,14 +473,18 @@
 						<&clk IMX8MM_CLK_AUDIO_AHB>,
 						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 						<&clk IMX8MM_SYS_PLL3>,
-						<&clk IMX8MM_VIDEO_PLL1>;
+						<&clk IMX8MM_VIDEO_PLL1>,
+						<&clk IMX8MM_AUDIO_PLL1>,
+						<&clk IMX8MM_AUDIO_PLL2>;
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
 				assigned-clock-rates = <0>,
 							<400000000>,
 							<400000000>,
 							<750000000>,
-							<594000000>;
+							<594000000>,
+							<393216000>,
+							<361267200>;
 			};
 
 			src: reset-controller@30390000 {
@@ -498,7 +496,7 @@
 		};
 
 		aips2: bus@30400000 {
-			compatible = "fsl,aips-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30400000 0x30400000 0x400000>;
@@ -557,7 +555,7 @@
 		};
 
 		aips3: bus@30800000 {
-			compatible = "fsl,aips-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x30800000 0x30800000 0x400000>;
@@ -638,6 +636,36 @@
 				status = "disabled";
 			};
 
+			crypto: crypto@30900000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x30900000 0x40000>;
+				ranges = <0 0x30900000 0x40000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_AHB>,
+					 <&clk IMX8MM_CLK_IPG_ROOT>;
+				clock-names = "aclk", "ipg";
+
+				sec_jr0: jr@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			i2c1: i2c@30a20000 {
 				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 				#address-cells = <1>;
@@ -698,8 +726,6 @@
 					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
-				assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
-				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -728,8 +754,6 @@
 					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
-				assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
-				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -737,11 +761,11 @@
 			};
 
 			sdma1: dma-controller@30bd0000 {
-				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 				reg = <0x30bd0000 0x10000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
-					 <&clk IMX8MM_CLK_SDMA1_ROOT>;
+					 <&clk IMX8MM_CLK_AHB>;
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
@@ -776,7 +800,7 @@
 		};
 
 		aips4: bus@32c00000 {
-			compatible = "fsl,aips-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
@@ -859,6 +883,16 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		ddrc: memory-controller@3d400000 {
+			compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+			reg = <0x3d400000 0x400000>;
+			clock-names = "core", "pll", "alt", "apb";
+			clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+				 <&clk IMX8MM_DRAM_PLL>,
+				 <&clk IMX8MM_CLK_DRAM_ALT>,
+				 <&clk IMX8MM_CLK_DRAM_APB>;
+		};
+
 		ddr-pmu@3d800000 {
 			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
 			reg = <0x3d800000 0x400000>;
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 8d61597e0c..4419679d4c 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
  * Copyright 2019 NXP
  */
 
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
 &{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
@@ -90,3 +98,7 @@
 &usdhc3 {
 	u-boot,dm-spl;
 };
+
+&wdog1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 4675ada0a0..24a93ac2d6 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -3,6 +3,14 @@
  * Copyright 2019 NXP
  */
 
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
 &{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
@@ -119,3 +127,7 @@
 &usdhc3 {
 	u-boot,dm-spl;
 };
+
+&wdog1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts
new file mode 100644
index 0000000000..4892ad5ee1
--- /dev/null
+++ b/arch/arm/dts/imx8mq-phanbell.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "Google i.MX8MQ Phanbell";
+	compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000 0 0x40000000>;
+	};
+
+	pmic_osc: clock-pmic {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic_osc";
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pmic@4b {
+		compatible = "rohm,bd71837";
+		reg = <0x4b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		#clock-cells = <0>;
+		clocks = <&pmic_osc>;
+		clock-output-names = "pmic_clk";
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 GPIO_ACTIVE_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <900000>;
+				rohm,dvs-idle-voltage = <900000>;
+				rohm,dvs-suspend-voltage = <800000>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-boot-on;
+				regulator-always-on;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3: BUCK3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				rohm,dvs-run-voltage = <900000>;
+			};
+
+			buck4: BUCK4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				rohm,dvs-run-voltage = <900000>;
+			};
+
+			buck5: BUCK5 {
+				regulator-name = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck7: BUCK7 {
+				regulator-name = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck8: BUCK8 {
+				regulator-name = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6: LDO6 {
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7: LDO7 {
+				regulator-name = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <50>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_pmic: pmicirq {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+		>;
+	};
+};
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 5ade63665a..b52565473d 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -26,6 +26,8 @@
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_IMX8MQ		0x82
+#define MXC_CPU_IMX8MD		0x83 /* dummy ID */
+#define MXC_CPU_IMX8MQL     0x84 /* dummy ID */
 #define MXC_CPU_IMX8MM		0x85 /* dummy ID */
 #define MXC_CPU_IMX8MML		0x86 /* dummy ID */
 #define MXC_CPU_IMX8MMD		0x87 /* dummy ID */
@@ -33,6 +35,11 @@
 #define MXC_CPU_IMX8MMS		0x89 /* dummy ID */
 #define MXC_CPU_IMX8MMSL	0x8a /* dummy ID */
 #define MXC_CPU_IMX8MN		0x8b /* dummy ID */
+#define MXC_CPU_IMX8MND		0x8c /* dummy ID */
+#define MXC_CPU_IMX8MNS		0x8d /* dummy ID */
+#define MXC_CPU_IMX8MNL		0x8e /* dummy ID */
+#define MXC_CPU_IMX8MNDL		0x8f /* dummy ID */
+#define MXC_CPU_IMX8MNSL		0x181 /* dummy ID */
 #define MXC_CPU_IMX8MP		0x182/* dummy ID */
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QM		0x91 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
index 8e1e9bbf43..c1a9c353ba 100644
--- a/arch/arm/include/asm/arch-imx8/sci/rpc.h
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -8,6 +8,11 @@
 #define SC_RPC_H
 
 /* Note: Check SCFW API Released DOC before you want to modify something */
+/* Defines */
+
+#define SCFW_API_VERSION_MAJOR  1U
+#define SCFW_API_VERSION_MINOR  15U
+
 #define SC_RPC_VERSION          1U
 
 #define SC_RPC_MAX_MSG          8U
@@ -17,9 +22,13 @@
 #define RPC_SVC(MSG)            ((MSG)->svc)
 #define RPC_FUNC(MSG)           ((MSG)->func)
 #define RPC_R8(MSG)             ((MSG)->func)
+#define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
+				  (s64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
 #define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
 #define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
+#define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
+				  (u64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
 #define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
 #define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
@@ -76,6 +85,8 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_REBOOT				9U
 #define PM_FUNC_REBOOT_PARTITION		12U
 #define PM_FUNC_CPU_START			11U
+#define PM_FUNC_CPU_RESET			23U
+#define PM_FUNC_RESOURCE_RESET			29U
 #define PM_FUNC_IS_PARTITION_STARTED 24U
 
 /* MISC RPC */
@@ -160,26 +171,59 @@ struct sc_rpc_msg_s {
 #define RM_FUNC_DUMP				27U
 
 /* SECO RPC */
-#define SECO_FUNC_UNKNOWN			0
-#define SECO_FUNC_IMAGE_LOAD			1U
-#define SECO_FUNC_AUTHENTICATE			2U
-#define SECO_FUNC_FORWARD_LIFECYCLE		3U
-#define SECO_FUNC_RETURN_LIFECYCLE		4U
-#define SECO_FUNC_COMMIT			5U
-#define SECO_FUNC_ATTEST_MODE			6U
-#define SECO_FUNC_ATTEST			7U
-#define SECO_FUNC_GET_ATTEST_PKEY		8U
-#define SECO_FUNC_GET_ATTEST_SIGN		9U
-#define SECO_FUNC_ATTEST_VERIFY			10U
-#define SECO_FUNC_GEN_KEY_BLOB			11U
-#define SECO_FUNC_LOAD_KEY			12U
-#define SECO_FUNC_GET_MP_KEY			13U
-#define SECO_FUNC_UPDATE_MPMR			14U
-#define SECO_FUNC_GET_MP_SIGN			15U
-#define SECO_FUNC_BUILD_INFO			16U
-#define SECO_FUNC_CHIP_INFO			17U
-#define SECO_FUNC_ENABLE_DEBUG			18U
-#define SECO_FUNC_GET_EVENT			19U
-#define SECO_FUNC_FUSE_WRITE			20U
+#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
+#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
+#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
+#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
+#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
+#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
+#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
+#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
+#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
+#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
+#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
+#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
+#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
+#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
+#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
+#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
+#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
+#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
+#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
+#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
+#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
+#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
+#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
+#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
+#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
+#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
+#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */
+
+/* IRQ RPC */
+#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
+#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
+#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
+
+/* TIMER RPC */
+#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
 
 #endif /* SC_RPC_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 14ee6f999b..05f736f14f 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -72,6 +72,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 		    sc_faddr_t address);
 sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
+int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
 
 /* MISC API */
 int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
@@ -108,6 +109,7 @@ int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
 
 /* PAD API */
 int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
+int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
 
 /* SMMU API */
 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
@@ -122,5 +124,13 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 			 sc_faddr_t export_addr, u16 max_size);
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
+int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+			u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
+int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
+int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
+			  u32 *data0, u32 *data1, u32 *data2, u32 *data3,
+			  u32 *data4, u8 size);
 
 #endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
index 905c56834e..df368e8c8b 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
@@ -6,6 +6,9 @@
 #ifndef SC_PAD_API_H
 #define SC_PAD_API_H
 
+/* Defines for type widths */
+#define SC_PAD_MUX_W            3U    /* Width of mux parameter */
+
 /* Defines for sc_pad_config_t */
 #define SC_PAD_CONFIG_NORMAL	0U	/* Normal */
 #define SC_PAD_CONFIG_OD	1U	/* Open Drain */
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
index 9eadc88592..adfed13e33 100644
--- a/arch/arm/include/asm/arch-imx8/sci/types.h
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -32,6 +32,7 @@ typedef u64 sc_ipc_t;
 #define SC_83MHZ         83333333U   /* 83MHz */
 #define SC_84MHZ         84375000U   /* 84.37MHz */
 #define SC_100MHZ       100000000U   /* 100MHz */
+#define SC_114MHZ       114000000U   /* 114MHz */
 #define SC_125MHZ       125000000U   /* 125MHz */
 #define SC_133MHZ       133333333U   /* 133MHz */
 #define SC_135MHZ       135000000U   /* 135MHz */
@@ -52,6 +53,7 @@ typedef u64 sc_ipc_t;
 #define SC_372MHZ       372000000U   /* 372MHz */
 #define SC_375MHZ       375000000U   /* 375MHz */
 #define SC_400MHZ       400000000U   /* 400MHz */
+#define SC_465MHZ       465000000U   /* 465MHz */
 #define SC_500MHZ       500000000U   /* 500MHz */
 #define SC_594MHZ       594000000U   /* 594MHz */
 #define SC_625MHZ       625000000U   /* 625MHz */
@@ -75,6 +77,7 @@ typedef u64 sc_ipc_t;
 #define SC_1500MHZ     1500000000U   /* 1.5GHz */
 #define SC_1600MHZ     1600000000U   /* 1.6GHz */
 #define SC_1800MHZ     1800000000U   /* 1.8GHz */
+#define SC_1860MHZ     1860000000U   /* 1.86GHz */
 #define SC_2000MHZ     2000000000U   /* 2.0GHz */
 #define SC_2112MHZ     2112000000U   /* 2.12GHz */
 
@@ -89,6 +92,7 @@ typedef u64 sc_ipc_t;
 #define SC_144MHZ       144000000U   /* 144MHz */
 #define SC_192MHZ       192000000U   /* 192MHz */
 #define SC_211MHZ       211200000U   /* 211.2MHz */
+#define SC_228MHZ       228000000U   /* 233MHz */
 #define SC_240MHZ       240000000U   /* 240MHz */
 #define SC_264MHZ       264000000U   /* 264MHz */
 #define SC_352MHZ       352000000U   /* 352MHz */
@@ -96,11 +100,13 @@ typedef u64 sc_ipc_t;
 #define SC_384MHZ       384000000U   /* 384MHz */
 #define SC_396MHZ       396000000U   /* 396MHz */
 #define SC_432MHZ       432000000U   /* 432MHz */
+#define SC_456MHZ       456000000U   /* 466MHz */
 #define SC_480MHZ       480000000U   /* 480MHz */
 #define SC_600MHZ       600000000U   /* 600MHz */
 #define SC_744MHZ       744000000U   /* 744MHz */
 #define SC_792MHZ       792000000U   /* 792MHz */
 #define SC_864MHZ       864000000U   /* 864MHz */
+#define SC_912MHZ       912000000U   /* 912MHz */
 #define SC_960MHZ       960000000U   /* 960MHz */
 #define SC_1056MHZ     1056000000U   /* 1056MHz */
 #define SC_1104MHZ     1104000000U   /* 1104MHz */
diff --git a/arch/arm/include/asm/arch-imx8/snvs_security_sc.h b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
new file mode 100644
index 0000000000..0b7ded7ba6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _SNVS_SECURITY_SC_H
+#define _SNVS_SECURITY_SC_H
+
+int snvs_security_sc_init(void);
+
+#endif /* _SNVS_SECURITY_SC_H */
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index debed6bac7..140e8bbabd 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -19,7 +19,7 @@
 
 #define LOCK_STATUS	BIT(31)
 #define LOCK_SEL_MASK	BIT(29)
-#define CLKE_MASK	BIT(11)
+#define CLKE_MASK	BIT(13)
 #define RST_MASK	BIT(9)
 #define BYPASS_MASK	BIT(4)
 #define	MDIV_SHIFT	12
@@ -363,7 +363,8 @@ enum clk_root_src {
 	EXT_CLK_2,
 	EXT_CLK_3,
 	EXT_CLK_4,
-	OSC_HDMI_CLK
+	OSC_HDMI_CLK,
+	ARM_A53_ALT_CLK,
 };
 
 enum clk_ccgr_index {
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 38a6f5966b..9dda6ddc8c 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -153,6 +153,7 @@ enum clk_root_src {
 	EXT_CLK_3,
 	EXT_CLK_4,
 	OSC_27M_CLK,
+	ARM_A53_ALT_CLK,
 };
 
 /* CCGR index */
@@ -419,7 +420,7 @@ enum clk_src_index {
 
 enum frac_pll_out_val {
 	FRAC_PLL_OUT_1000M,
-	FRAC_PLL_OUT_1600M,
+	FRAC_PLL_OUT_800M,
 };
 
 void init_nand_clk(void);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 35b39b1f86..2a997f280d 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -16,7 +16,7 @@
 #define is_soc_rev(rev) (soc_rev() == rev)
 
 /* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define cpu_type(rev) (((rev) >> 12) & 0x1ff)
 #define soc_type(rev) (((rev) >> 12) & 0xf0)
 /* both macros return/take MXC_CPU_ constants */
 #define get_cpu_type() (cpu_type(get_cpu_rev()))
@@ -37,13 +37,15 @@
 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
-#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
-#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
+#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
+#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
 	is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
@@ -53,7 +55,14 @@
 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
-#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN))
+#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
+	is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
+	is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
+#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
+#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
+#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
+#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
+#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP))
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8482f5446c..b839aa7a50 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -57,7 +57,7 @@ obj-y	+= interrupts_64.o
 else
 obj-y	+= interrupts.o
 endif
-ifndef CONFIG_SYSRESET
+ifndef CONFIG_$(SPL_TPL_)SYSRESET
 obj-y	+= reset.o
 endif
 
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index bfa85c64c6..e83f6934cd 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -95,7 +95,17 @@ const char *get_imx_type(u32 imxtype)
 	case MXC_CPU_IMX8MP:
 		return "8MP";	/* Quad-core version of the imx8mp */
 	case MXC_CPU_IMX8MN:
-		return "8MNano";/* Quad-core version of the imx8mn */
+		return "8MNano Quad"; /* Quad-core version */
+	case MXC_CPU_IMX8MND:
+		return "8MNano Dual"; /* Dual-core version */
+	case MXC_CPU_IMX8MNS:
+		return "8MNano Solo"; /* Single-core version */
+	case MXC_CPU_IMX8MNL:
+		return "8MNano QuadLite"; /* Quad-core Lite version */
+	case MXC_CPU_IMX8MNDL:
+		return "8MNano DualLite"; /* Dual-core Lite version */
+	case MXC_CPU_IMX8MNSL:
+		return "8MNano SoloLite"; /* Single-core Lite version */
 	case MXC_CPU_IMX8MM:
 		return "8MMQ";	/* Quad-core version of the imx8mm */
 	case MXC_CPU_IMX8MML:
@@ -109,7 +119,11 @@ const char *get_imx_type(u32 imxtype)
 	case MXC_CPU_IMX8MMSL:
 		return "8MMSL";	/* Single-core Lite version of the imx8mm */
 	case MXC_CPU_IMX8MQ:
-		return "8MQ";	/* Quad-core version of the imx8m */
+		return "8MQ";	/* Quad-core version of the imx8mq */
+	case MXC_CPU_IMX8MQL:
+		return "8MQLite";	/* Quad-core Lite version of the imx8mq */
+	case MXC_CPU_IMX8MD:
+		return "8MD";	/* Dual-core version of the imx8mq */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -314,6 +328,7 @@ enum cpu_speed {
 	OCOTP_TESTER3_SPEED_GRADE1,
 	OCOTP_TESTER3_SPEED_GRADE2,
 	OCOTP_TESTER3_SPEED_GRADE3,
+	OCOTP_TESTER3_SPEED_GRADE4,
 };
 
 u32 get_cpu_speed_grade_hz(void)
@@ -326,17 +341,28 @@ u32 get_cpu_speed_grade_hz(void)
 
 	val = readl(&fuse->tester3);
 	val >>= OCOTP_TESTER3_SPEED_SHIFT;
-	val &= 0x3;
+
+	if (is_imx8mn() || is_imx8mp()) {
+		val &= 0xf;
+		return 2300000000 - val * 100000000;
+	}
+
+	if (is_imx8mm())
+		val &= 0x7;
+	else
+		val &= 0x3;
 
 	switch(val) {
 	case OCOTP_TESTER3_SPEED_GRADE0:
 		return 800000000;
 	case OCOTP_TESTER3_SPEED_GRADE1:
-		return is_mx7() ? 500000000 : 1000000000;
+		return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
 	case OCOTP_TESTER3_SPEED_GRADE2:
-		return is_mx7() ? 1000000000 : 1300000000;
+		return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
 	case OCOTP_TESTER3_SPEED_GRADE3:
-		return is_mx7() ? 1200000000 : 1500000000;
+		return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
+	case OCOTP_TESTER3_SPEED_GRADE4:
+		return 2000000000;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 5827ab334f..1f8add015f 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -90,4 +90,17 @@ source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
 source "board/siemens/capricorn/Kconfig"
 
+config IMX_SNVS_SEC_SC
+	bool "Support SNVS configuration"
+	help
+	  Allow to configure the SNVS via SCU API to configure tampers and secure
+	  violation.
+
+config IMX_SNVS_SEC_SC_AUTO
+	bool "Support SNVS configuration command"
+	depends on IMX_SNVS_SEC_SC
+	help
+	  This configuration will apply the selected configurations automatically
+	  at boot.
+
 endif
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 7ffb7e95b2..bbb41adbe4 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_AHAB_BOOT) += ahab.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
 endif
+obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index cf3c7d762a..6d25abe5ce 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -75,7 +75,7 @@ int authenticate_os_container(ulong addr)
 	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
 	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
 
-	err = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
 				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
 	if (err) {
 		printf("Authenticate container hdr failed, return %d\n",
@@ -90,22 +90,21 @@ int authenticate_os_container(ulong addr)
 					    sizeof(struct container_hdr) +
 					    i * sizeof(struct boot_img_t));
 
-		debug("img %d, dst 0x%llx, src 0x%lx, size 0x%x\n",
-		      i, img->dst, img->offset + addr, img->size);
+		debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
+		      i, (uint32_t) img->dst, img->offset + addr, img->size);
 
 		memcpy((void *)img->dst, (const void *)(img->offset + addr),
 		       img->size);
 
 		s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
-		e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE);
+		e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
 
 		flush_dcache_range(s, e);
 
 		/* Find the memreg and set permission for seco pt */
 		err = sc_rm_find_memreg(-1, &mr, s, e);
 		if (err) {
-			printf("Not found memreg for image: %d, error %d\n",
-			       i, err);
+			printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err);
 			ret = -ENOMEM;
 			goto exit;
 		}
@@ -123,7 +122,7 @@ int authenticate_os_container(ulong addr)
 			goto exit;
 		}
 
-		err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+		err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
 					   (1 << i));
 		if (err) {
 			printf("Authenticate img %d failed, return %d\n",
@@ -144,7 +143,7 @@ int authenticate_os_container(ulong addr)
 	}
 
 exit:
-	if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE)
+	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE)
 		printf("Error: release container failed!\n");
 
 	return ret;
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
index 00fe4670bb..76d6571d8b 100644
--- a/arch/arm/mach-imx/imx8/misc.c
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -2,6 +2,7 @@
 #include <common.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/mach-imx/sys_proto.h>
+#include <imx_sip.h>
 
 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 {
@@ -26,9 +27,6 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 	return 0;
 }
 
-#define FSL_SIP_BUILDINFO			0xC2000003
-#define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
-
 void build_info(void)
 {
 	u32 seco_build = 0, seco_commit = 0;
@@ -51,8 +49,8 @@ void build_info(void)
 	}
 
 	/* Get ARM Trusted Firmware commit id */
-	atf_commit = call_imx_sip(FSL_SIP_BUILDINFO,
-				  FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+	atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
+				  IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
 	if (atf_commit == 0xffffffff) {
 		debug("ATF does not support build info\n");
 		atf_commit = 0x30; /* Display 0 */
diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c
index b57e68e412..cc8a51ad55 100644
--- a/arch/arm/mach-imx/imx8/parse-container.c
+++ b/arch/arm/mach-imx/imx8/parse-container.c
@@ -23,23 +23,23 @@ static int authenticate_image(struct boot_img_t *img, int image_index)
 	int err;
 	int ret = 0;
 
-	debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
-	      image_index, img->dst, img->offset, img->size);
+	debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
+	      image_index, (uint32_t)img->dst, img->offset, img->size);
 
 	/* Find the memreg and set permission for seco pt */
 	err = sc_rm_find_memreg(-1, &mr,
 				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
-				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE));
+				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
 
 	if (err) {
-		printf("can't find memreg for image: %d, err %d\n",
-		       image_index, err);
+		printf("can't find memreg for image %d load address 0x%x, error %d\n",
+		       image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err);
 		return -ENOMEM;
 	}
 
 	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
 	if (!err)
-		debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+		debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
 
 	err = sc_rm_set_memreg_permissions(-1, mr,
 					   SECO_PT, SC_RM_PERM_FULL);
@@ -49,7 +49,7 @@ static int authenticate_image(struct boot_img_t *img, int image_index)
 		return -EPERM;
 	}
 
-	err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE,
+	err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
 				   1 << image_index);
 	if (err) {
 		printf("authenticate img %d failed, return %d\n",
@@ -168,7 +168,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
 	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
 	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
 
-	ret = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER,
+	ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
 				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
 	if (ret) {
 		printf("authenticate container hdr failed, return %d\n", ret);
@@ -194,7 +194,7 @@ static int read_auth_container(struct spl_image_info *spl_image,
 
 end_auth:
 #ifdef CONFIG_AHAB_BOOT
-	if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0))
+	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
 		printf("Error: release container failed!\n");
 #endif
 	return ret;
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
new file mode 100644
index 0000000000..73f5651161
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP.
+ */
+
+/*
+ * Configuration of the Tamper pins in different mode:
+ *  - default (no tamper pins): _default_
+ *  - passive mode expecting VCC on the line: "_passive_vcc_"
+ *  - passive mode expecting VCC on the line: "_passive_gnd_"
+ *  - active mode: "_active_"
+ */
+
+#include <command.h>
+#include <log.h>
+#include <stddef.h>
+#include <common.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch-imx8/imx8-pins.h>
+#include <asm/arch-imx8/snvs_security_sc.h>
+
+/* Access to gd */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SC_WRITE_CONF 1
+
+#define PGD_HEX_VALUE 0x41736166
+#define SRTC_EN 0x1
+#define DP_EN BIT(5)
+
+struct snvs_security_sc_conf {
+	struct snvs_hp_conf {
+		u32 lock;		/* HPLR - HP Lock */
+		u32 __cmd;		/* HPCOMR - HP Command */
+		u32 __ctl;		/* HPCR - HP Control */
+		u32 secvio_intcfg;	/* HPSICR - Security Violation Int
+					 * Config
+					 */
+		u32 secvio_ctl;		/* HPSVCR - Security Violation Control*/
+		u32 status;		/* HPSR - HP Status */
+		u32 secvio_status;	/* HPSVSR - Security Violation Status */
+		u32 __ha_counteriv;	/* High Assurance Counter IV */
+		u32 __ha_counter;		/* High Assurance Counter */
+		u32 __rtc_msb;		/* Real Time Clock/Counter MSB */
+		u32 __rtc_lsb;		/* Real Time Counter LSB */
+		u32 __time_alarm_msb;	/* Time Alarm MSB */
+		u32 __time_alarm_lsb;	/* Time Alarm LSB */
+	} hp;
+	struct snvs_lp_conf {
+		u32 lock;
+		u32 __ctl;
+		u32 __mstr_key_ctl;	/* Master Key Control */
+		u32 secvio_ctl;		/* Security Violation Control */
+		u32 tamper_filt_cfg;	/* Tamper Glitch Filters Configuration*/
+		u32 tamper_det_cfg;	/* Tamper Detectors Configuration */
+		u32 status;
+		u32 __srtc_msb;		/* Secure Real Time Clock/Counter MSB */
+		u32 __srtc_lsb;		/* Secure Real Time Clock/Counter LSB */
+		u32 __time_alarm;		/* Time Alarm */
+		u32 __smc_msb;		/* Secure Monotonic Counter MSB */
+		u32 __smc_lsb;		/* Secure Monotonic Counter LSB */
+		u32 __pwr_glitch_det;	/* Power Glitch Detector */
+		u32 __gen_purpose;
+		u8 __zmk[32];		/* Zeroizable Master Key */
+		u32 __rsvd0;
+		u32 __gen_purposes[4];	/* gp0_30 to gp0_33 */
+		u32 tamper_det_cfg2;	/* Tamper Detectors Configuration2 */
+		u32 tamper_det_status;	/* Tamper Detectors status */
+		u32 tamper_filt1_cfg;	/* Tamper Glitch Filter1 Configuration*/
+		u32 tamper_filt2_cfg;	/* Tamper Glitch Filter2 Configuration*/
+		u32 __rsvd1[4];
+		u32 act_tamper1_cfg;	/* Active Tamper1 Configuration */
+		u32 act_tamper2_cfg;	/* Active Tamper2 Configuration */
+		u32 act_tamper3_cfg;	/* Active Tamper3 Configuration */
+		u32 act_tamper4_cfg;	/* Active Tamper4 Configuration */
+		u32 act_tamper5_cfg;	/* Active Tamper5 Configuration */
+		u32 __rsvd2[3];
+		u32 act_tamper_ctl;	/* Active Tamper Control */
+		u32 act_tamper_clk_ctl;	/* Active Tamper Clock Control */
+		u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
+		u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
+	} lp;
+};
+
+static struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_ctl = 0x3000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_ctl = 0x3000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_ctl = 0x3000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_ctl = 0x3000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
+		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x00010001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static struct snvs_security_sc_conf *get_snvs_config(void)
+{
+	return &snvs_default_config;
+}
+
+struct snvs_dgo_conf {
+	u32 tamper_offset_ctl;
+	u32 tamper_pull_ctl;
+	u32 tamper_ana_test_ctl;
+	u32 tamper_sensor_trim_ctl;
+	u32 tamper_misc_ctl;
+	u32 tamper_core_volt_mon_ctl;
+};
+
+static struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct snvs_dgo_conf *get_snvs_dgo_config(void)
+{
+	return &snvs_dgo_default_config;
+}
+
+struct tamper_pin_cfg {
+	u32 pad;
+	u32 mux_conf;
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+	{SC_P_CSI_D00, 0}, /* Tamp_Out0 */
+	{SC_P_CSI_D01, 0}, /* Tamp_Out1 */
+	{SC_P_CSI_D02, 0}, /* Tamp_Out2 */
+	{SC_P_CSI_D03, 0}, /* Tamp_Out3 */
+	{SC_P_CSI_D04, 0}, /* Tamp_Out4 */
+	{SC_P_CSI_D05, 0}, /* Tamp_In0 */
+	{SC_P_CSI_D06, 0}, /* Tamp_In1 */
+	{SC_P_CSI_D07, 0}, /* Tamp_In2 */
+	{SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
+	{SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+	{SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+#define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config
+
+static struct tamper_pin_cfg *get_tamper_pin_cfg_list(u32 *size)
+{
+	*size = sizeof(TAMPER_PIN_LIST_CHOSEN) /
+		sizeof(TAMPER_PIN_LIST_CHOSEN[0]);
+
+	return TAMPER_PIN_LIST_CHOSEN;
+}
+
+#define SC_CONF_OFFSET_OF(_field) \
+	(offsetof(struct snvs_security_sc_conf, _field))
+
+static u32 ptr_value(u32 *_p)
+{
+	return (_p) ? *_p : 0xdeadbeef;
+}
+
+static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
+				     u32 *_p3, u32 *_p4, u32 *_p5,
+				     u32 _cnt)
+{
+	int scierr = 0;
+	u32 d1 = ptr_value(_p1);
+	u32 d2 = ptr_value(_p2);
+	u32 d3 = ptr_value(_p3);
+	u32 d4 = ptr_value(_p4);
+	u32 d5 = ptr_value(_p5);
+
+	scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
+				       &d4, &d4, _cnt);
+	if (scierr != SC_ERR_NONE) {
+		printf("Failed to set secvio configuration\n");
+		debug("Failed to set conf id 0x%x with values ", id);
+		debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
+		      d1, d2, d3, d4, d5, _cnt);
+		goto exit;
+	}
+
+	if (_p1)
+		*(u32 *)_p1 = d1;
+	if (_p2)
+		*(u32 *)_p2 = d2;
+	if (_p3)
+		*(u32 *)_p3 = d3;
+	if (_p4)
+		*(u32 *)_p4 = d4;
+	if (_p5)
+		*(u32 *)_p5 = d5;
+
+exit:
+	return scierr;
+}
+
+#define SC_CHECK_WRITE1(id, _p1) \
+	check_write_secvio_config(id, _p1, NULL, NULL, NULL, NULL, 1)
+
+static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
+{
+	int scierr = 0;
+
+	debug("%s\n", __func__);
+
+	debug("Applying config:\n"
+		  "\thp.lock = 0x%.8x\n"
+		  "\thp.secvio_ctl = 0x%.8x\n"
+		  "\tlp.lock = 0x%.8x\n"
+		  "\tlp.secvio_ctl = 0x%.8x\n"
+		  "\tlp.tamper_filt_cfg = 0x%.8x\n"
+		  "\tlp.tamper_det_cfg = 0x%.8x\n"
+		  "\tlp.tamper_det_cfg2 = 0x%.8x\n"
+		  "\tlp.tamper_filt1_cfg = 0x%.8x\n"
+		  "\tlp.tamper_filt2_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper1_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper2_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper3_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper4_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper5_cfg = 0x%.8x\n"
+		  "\tlp.act_tamper_ctl = 0x%.8x\n"
+		  "\tlp.act_tamper_clk_ctl = 0x%.8x\n"
+		  "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n"
+		  "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n",
+			cnf->hp.lock,
+			cnf->hp.secvio_ctl,
+			cnf->lp.lock,
+			cnf->lp.secvio_ctl,
+			cnf->lp.tamper_filt_cfg,
+			cnf->lp.tamper_det_cfg,
+			cnf->lp.tamper_det_cfg2,
+			cnf->lp.tamper_filt1_cfg,
+			cnf->lp.tamper_filt2_cfg,
+			cnf->lp.act_tamper1_cfg,
+			cnf->lp.act_tamper2_cfg,
+			cnf->lp.act_tamper3_cfg,
+			cnf->lp.act_tamper4_cfg,
+			cnf->lp.act_tamper5_cfg,
+			cnf->lp.act_tamper_ctl,
+			cnf->lp.act_tamper_clk_ctl,
+			cnf->lp.act_tamper_routing_ctl1,
+			cnf->lp.act_tamper_routing_ctl2);
+
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
+					   &cnf->lp.tamper_filt_cfg,
+					   &cnf->lp.tamper_filt1_cfg,
+					   &cnf->lp.tamper_filt2_cfg, NULL,
+					   NULL, 3);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Configure AT */
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
+					   &cnf->lp.act_tamper1_cfg,
+					   &cnf->lp.act_tamper2_cfg,
+					   &cnf->lp.act_tamper2_cfg,
+					   &cnf->lp.act_tamper2_cfg,
+					   &cnf->lp.act_tamper2_cfg, 5);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Configure AT routing */
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
+					   &cnf->lp.act_tamper_routing_ctl1,
+					   &cnf->lp.act_tamper_routing_ctl2,
+					   NULL, NULL, NULL, 2);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Configure AT frequency */
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
+				 &cnf->lp.act_tamper_clk_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Activate the ATs */
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
+				 &cnf->lp.act_tamper_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Activate the detectors */
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
+					   &cnf->lp.tamper_det_cfg,
+					   &cnf->lp.tamper_det_cfg2, NULL, NULL,
+					   NULL, 2);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Configure LP secvio */
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
+				 &cnf->lp.secvio_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Configure HP secvio */
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
+				 &cnf->hp.secvio_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Lock access */
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+exit:
+	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
+{
+	int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
+
+	if (scierr != SC_ERR_NONE) {
+		printf("Failed to set dgo configuration\n");
+		debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
+	}
+
+	return scierr;
+}
+
+static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
+{
+	int scierr = 0;
+
+	debug("%s\n", __func__);
+
+	debug("Applying config:\n"
+		"\ttamper_offset_ctl = 0x%.8x\n"
+		"\ttamper_pull_ctl = 0x%.8x\n"
+		"\ttamper_ana_test_ctl = 0x%.8x\n"
+		"\ttamper_sensor_trim_ctl = 0x%.8x\n"
+		"\ttamper_misc_ctl = 0x%.8x\n"
+		"\ttamper_core_volt_mon_ctl = 0x%.8x\n",
+			cnf->tamper_offset_ctl,
+			cnf->tamper_pull_ctl,
+			cnf->tamper_ana_test_ctl,
+			cnf->tamper_sensor_trim_ctl,
+			cnf->tamper_misc_ctl,
+			cnf->tamper_core_volt_mon_ctl);
+
+	dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	/* Last as it could lock the writes */
+	dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+exit:
+	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+static int pad_write(u32 _pad, u32 _value)
+{
+	int scierr = sc_pad_set(-1, _pad, _value);
+
+	if (scierr != SC_ERR_NONE) {
+		printf("Failed to set pad configuration\n");
+		debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
+	}
+
+	return scierr;
+}
+
+static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
+{
+	int scierr = 0;
+	u32 idx;
+
+	debug("%s\n", __func__);
+
+	for (idx = 0; idx < size; idx++) {
+		debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
+		      confs[idx].mux_conf);
+		pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
+		if (scierr != SC_ERR_NONE)
+			goto exit;
+	}
+
+exit:
+	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+}
+
+int examples(void)
+{
+	u32 size;
+	struct snvs_security_sc_conf *snvs_conf;
+	struct snvs_dgo_conf *snvs_dgo_conf;
+	struct tamper_pin_cfg *tamper_pin_conf;
+
+	/* Caller */
+	snvs_conf = get_snvs_config();
+	snvs_dgo_conf = get_snvs_dgo_config();
+	tamper_pin_conf = get_tamper_pin_cfg_list(&size);
+
+	/* Default */
+	snvs_conf = &snvs_default_config;
+	snvs_dgo_conf = &snvs_dgo_default_config;
+	tamper_pin_conf = tamper_pin_list_default_config;
+
+	/* Passive tamper expecting VCC on the line */
+	snvs_conf = &snvs_passive_vcc_config;
+	snvs_dgo_conf = &snvs_dgo_passive_vcc_config;
+	tamper_pin_conf = tamper_pin_list_passive_vcc_config;
+
+	/* Passive tamper expecting GND on the line */
+	snvs_conf = &snvs_passive_gnd_config;
+	snvs_dgo_conf = &snvs_dgo_passive_gnd_config;
+	tamper_pin_conf = tamper_pin_list_passive_gnd_config;
+
+	/* Active tamper */
+	snvs_conf = &snvs_active_config;
+	snvs_dgo_conf = &snvs_dgo_active_config;
+	tamper_pin_conf = tamper_pin_list_active_config;
+
+	return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf;
+}
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+int snvs_security_sc_init(void)
+{
+	int err = 0;
+
+	struct snvs_security_sc_conf *snvs_conf;
+	struct snvs_dgo_conf *snvs_dgo_conf;
+	struct tamper_pin_cfg *tamper_pin_conf;
+	u32 size;
+
+	debug("%s\n", __func__);
+
+	snvs_conf = get_snvs_config();
+	snvs_dgo_conf = get_snvs_dgo_config();
+
+	tamper_pin_conf = get_tamper_pin_cfg_list(&size);
+
+	err = apply_tamper_pin_list_config(tamper_pin_conf, size);
+	if (err) {
+		debug("Failed to set pins\n");
+		goto exit;
+	}
+
+	err = apply_snvs_dgo_config(snvs_dgo_conf);
+	if (err) {
+		debug("Failed to set dgo\n");
+		goto exit;
+	}
+
+	err = apply_snvs_config(snvs_conf);
+	if (err) {
+		debug("Failed to set snvs\n");
+		goto exit;
+	}
+
+exit:
+	return err;
+}
+#endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */
+
+static char snvs_cfg_help_text[] =
+	"snvs_cfg\n"
+	"\thp.lock\n"
+	"\thp.secvio_ctl\n"
+	"\tlp.lock\n"
+	"\tlp.secvio_ctl\n"
+	"\tlp.tamper_filt_cfg\n"
+	"\tlp.tamper_det_cfg\n"
+	"\tlp.tamper_det_cfg2\n"
+	"\tlp.tamper_filt1_cfg\n"
+	"\tlp.tamper_filt2_cfg\n"
+	"\tlp.act_tamper1_cfg\n"
+	"\tlp.act_tamper2_cfg\n"
+	"\tlp.act_tamper3_cfg\n"
+	"\tlp.act_tamper4_cfg\n"
+	"\tlp.act_tamper5_cfg\n"
+	"\tlp.act_tamper_ctl\n"
+	"\tlp.act_tamper_clk_ctl\n"
+	"\tlp.act_tamper_routing_ctl1\n"
+	"\tlp.act_tamper_routing_ctl2\n"
+	"\n"
+	"ALL values should be in hexadecimal format";
+
+#define NB_REGISTERS 18
+static int do_snvs_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int err = 0;
+	u32 idx = 0;
+
+	struct snvs_security_sc_conf conf = {0};
+
+	if (argc != (NB_REGISTERS + 1))
+		return CMD_RET_USAGE;
+
+	conf.hp.lock = simple_strtoul(argv[++idx], NULL, 16);
+	conf.hp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.lock = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_filt_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_det_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_det_cfg2 = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_filt1_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_filt2_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper1_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper2_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper3_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper4_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper5_cfg = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper_clk_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper_routing_ctl1 = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.act_tamper_routing_ctl2 = simple_strtoul(argv[++idx], NULL, 16);
+
+	err = apply_snvs_config(&conf);
+
+	return err;
+}
+
+U_BOOT_CMD(snvs_cfg,
+	   NB_REGISTERS + 1, 1, do_snvs_cfg,
+	   "Security violation configuration",
+	   snvs_cfg_help_text
+);
+
+static char snvs_dgo_cfg_help_text[] =
+	"snvs_dgo_cfg\n"
+	"\ttamper_offset_ctl\n"
+	"\ttamper_pull_ctl\n"
+	"\ttamper_ana_test_ctl\n"
+	"\ttamper_sensor_trim_ctl\n"
+	"\ttamper_misc_ctl\n"
+	"\ttamper_core_volt_mon_ctl\n"
+	"\n"
+	"ALL values should be in hexadecimal format";
+
+static int do_snvs_dgo_cfg(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	int err = 0;
+	u32 idx = 0;
+
+	struct snvs_dgo_conf conf = {0};
+
+	if (argc != (6 + 1))
+		return CMD_RET_USAGE;
+
+	conf.tamper_offset_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.tamper_pull_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.tamper_ana_test_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.tamper_sensor_trim_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.tamper_misc_ctl = simple_strtoul(argv[++idx], NULL, 16);
+	conf.tamper_core_volt_mon_ctl = simple_strtoul(argv[++idx], NULL, 16);
+
+	err = apply_snvs_dgo_config(&conf);
+
+	return err;
+}
+
+U_BOOT_CMD(snvs_dgo_cfg,
+	   7, 1, do_snvs_dgo_cfg,
+	   "SNVS DGO configuration",
+	   snvs_dgo_cfg_help_text
+);
+
+static char tamper_pin_cfg_help_text[] =
+	"snvs_dgo_cfg\n"
+	"\tpad\n"
+	"\tvalue\n"
+	"\n"
+	"ALL values should be in hexadecimal format";
+
+static int do_tamper_pin_cfg(cmd_tbl_t *cmdtp, int flag, int argc,
+			     char *const argv[])
+{
+	int err = 0;
+	u32 idx = 0;
+
+	struct tamper_pin_cfg conf = {0};
+
+	if (argc != (2 + 1))
+		return CMD_RET_USAGE;
+
+	conf.pad = simple_strtoul(argv[++idx], NULL, 10);
+	conf.mux_conf = simple_strtoul(argv[++idx], NULL, 16);
+
+	err = apply_tamper_pin_list_config(&conf, 1);
+
+	return err;
+}
+
+U_BOOT_CMD(tamper_pin_cfg,
+	   3, 1, do_tamper_pin_cfg,
+	   "tamper pin configuration",
+	   tamper_pin_cfg_help_text
+);
+
+static char snvs_clear_status_help_text[] =
+	"snvs_clear_status\n"
+	"\tHPSR\n"
+	"\tHPSVSR\n"
+	"\tLPSR\n"
+	"\tLPTDSR\n"
+	"\n"
+	"Write the status registers with the value provided,"
+	" clearing the status";
+
+static int do_snvs_clear_status(cmd_tbl_t *cmdtp, int flag, int argc,
+				  char *const argv[])
+{
+	int scierr = 0;
+	u32 idx = 0;
+
+	struct snvs_security_sc_conf conf = {0};
+
+	if (argc != (2 + 1))
+		return CMD_RET_USAGE;
+
+	conf.lp.status = simple_strtoul(argv[++idx], NULL, 16);
+	conf.lp.tamper_det_status = simple_strtoul(argv[++idx], NULL, 16);
+
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
+					   &conf.lp.status, NULL, NULL, NULL,
+					   NULL, 1);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
+					   &conf.lp.tamper_det_status, NULL,
+					   NULL, NULL, NULL, 1);
+	if (scierr != SC_ERR_NONE)
+		goto exit;
+
+exit:
+	return (scierr == SC_ERR_NONE) ? 0 : 1;
+}
+
+U_BOOT_CMD(snvs_clear_status,
+	   3, 1, do_snvs_clear_status,
+	   "snvs clear status",
+	   snvs_clear_status_help_text
+);
+
+static char snvs_sec_status_help_text[] =
+	"snvs_sec_status\n"
+	"Display information about the security related to tamper and secvio";
+
+static int do_snvs_sec_status(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	int scierr;
+	u32 idx;
+
+	u32 data[5];
+
+	u32 pads[] = {
+		SC_P_CSI_D00,
+		SC_P_CSI_D01,
+		SC_P_CSI_D02,
+		SC_P_CSI_D03,
+		SC_P_CSI_D04,
+		SC_P_CSI_D05,
+		SC_P_CSI_D06,
+		SC_P_CSI_D07,
+		SC_P_CSI_HSYNC,
+		SC_P_CSI_VSYNC,
+	};
+
+	u32 fuses[] = {
+		14,
+		30,
+		31,
+		260,
+		261,
+		262,
+		263,
+		768,
+	};
+
+	struct snvs_reg {
+		u32 id;
+		u32 nb;
+	} snvs[] = {
+		/* Locks */
+		{0x0,  1},
+		{0x34, 1},
+		/* Security violation */
+		{0xc,  1},
+		{0x10, 1},
+		{0x18, 1},
+		{0x40, 1},
+		/* Temper detectors */
+		{0x48, 2},
+		{0x4c, 1},
+		{0xa4, 1},
+		/* */
+		{0x44, 3},
+		{0xe0, 1},
+		{0xe4, 1},
+		{0xe8, 2},
+		/* Misc */
+		{0x3c, 1},
+		{0x5c, 2},
+		{0x64, 1},
+		{0xf8, 2},
+	};
+
+	u32 dgo[] = {
+		0x0,
+		0x10,
+		0x20,
+		0x30,
+		0x40,
+		0x50,
+	};
+
+	/* Pins */
+	printf("Pins:\n");
+	for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
+		u8 pad_id = pads[idx];
+
+		scierr = sc_pad_get(-1, pad_id, &data[0]);
+		if (scierr == 0)
+			printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
+		else
+			printf("Failed to read Pin %d\n", pad_id);
+	}
+
+	/* Fuses */
+	printf("Fuses:\n");
+	for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
+		u32 fuse_id = fuses[idx];
+
+		scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
+		if (scierr == 0)
+			printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
+		else
+			printf("Failed to read Fuse %d\n", fuse_id);
+	}
+
+	/* SNVS */
+	printf("SNVS:\n");
+	for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
+		struct snvs_reg *reg = &snvs[idx];
+
+		scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
+					       &data[1], &data[2], &data[3],
+					       &data[4], reg->nb);
+		if (scierr == 0) {
+			int subidx;
+
+			printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
+			for (subidx = 0; subidx < reg->nb; subidx++)
+				printf(" %.8x", data[subidx]);
+			printf("\n");
+		} else {
+			printf("Failed to read SNVS %d\n", reg->id);
+		}
+	}
+
+	/* DGO */
+	printf("DGO:\n");
+	for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
+		u8 dgo_id = dgo[idx];
+
+		scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
+		if (scierr == 0)
+			printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
+		else
+			printf("Failed to read DGO %d\n", dgo_id);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(snvs_sec_status,
+	   1, 1, do_snvs_sec_status,
+	   "tamper pin configuration",
+	   snvs_sec_status_help_text
+);
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 58f1758ab6..895f903780 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -32,6 +32,11 @@ config TARGET_IMX8MQ_EVK
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_PHANBELL
+        bool "imx8mq_phanbell"
+        select IMX8MQ
+        select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_EVK
 	bool "imx8mm LPDDR4 EVK board"
 	select IMX8MM
@@ -62,6 +67,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
 source "board/freescale/imx8mn_evk/Kconfig"
 source "board/freescale/imx8mp_evk/Kconfig"
+source "board/google/imx8mq_phanbell/Kconfig"
 source "board/toradex/verdin-imx8mm/Kconfig"
 
 endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index c423ac0058..91c827f6c0 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll)
 	}
 
 	/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
-	if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+	if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
 		return 0;
 
-	if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+	if ((pll_gnrl_ctl & RST_MASK) == 0)
 		return 0;
 	/*
 	 * When BYPASS is equal to 1, PLL enters the bypass mode
 	 * regardless of the values of RESETB
 	 */
-	if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+	if (pll_gnrl_ctl & BYPASS_MASK)
 		return 24000000u;
 
-	if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+	if (!(pll_gnrl_ctl & LOCK_STATUS)) {
 		puts("pll not locked\n");
 		return 0;
 	}
 
-	if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
+	if (!(pll_gnrl_ctl & CLKE_MASK))
 		return 0;
 
-	main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
-		INTPLL_MAIN_DIV_SHIFT;
-	pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
-		INTPLL_PRE_DIV_SHIFT;
-	post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
-		INTPLL_POST_DIV_SHIFT;
+	main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
+		MDIV_SHIFT;
+	pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
+		PDIV_SHIFT;
+	post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
+		SDIV_SHIFT;
 
-	k = pll_fdiv_ctl1 & GENMASK(15, 0);
+	k = pll_fdiv_ctl1 & KDIV_MASK;
 
 	return lldiv((main_div * 65536 + k) * 24000000ULL,
 		     65536 * pre_div * (1 << post_div));
@@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk)
 
 	return 0;
 }
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+	u32 target;
+	u32 enet1_ref;
+
+	switch (type) {
+	case ENET_125MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+		break;
+	case ENET_50MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+		break;
+	case ENET_25MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* disable the clock first */
+	clock_enable(CCGR_ENET1, 0);
+	clock_enable(CCGR_SIM_ENET, 0);
+
+	/* set enet axi clock 266Mhz */
+	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON | enet1_ref |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON |
+		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+	/* enable clock */
+	clock_enable(CCGR_SIM_ENET, 1);
+	clock_enable(CCGR_ENET1, 1);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index aad9cf13ef..ee18cdee50 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -15,6 +15,8 @@
 
 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 
+static u32 get_root_clk(enum clk_root_index clock_id);
+
 static u32 decode_frac_pll(enum clk_root_src frac_pll)
 {
 	u32 pll_cfg0, pll_cfg1, pllout;
@@ -275,6 +277,8 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
 	case SYSTEM_PLL2_50M_CLK:
 	case SYSTEM_PLL3_CLK:
 		return decode_sscg_pll(root_src);
+	case ARM_A53_ALT_CLK:
+		return get_root_clk(ARM_A53_CLK_ROOT);
 	default:
 		return 0;
 	}
@@ -322,13 +326,26 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 	return 0;
 }
 
+u32 get_arm_core_clk(void)
+{
+	enum clk_root_src root_src;
+	u32 root_src_clk;
+
+	if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
+		return 0;
+
+	root_src_clk = get_root_src_clk(root_src);
+
+	return root_src_clk;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	u32 val;
 
-	switch(clk) {
+	switch (clk) {
 	case MXC_ARM_CLK:
-		return get_root_clk(ARM_A53_CLK_ROOT);
+		return get_arm_core_clk();
 	case MXC_IPG_CLK:
 		clock_get_target_val(IPG_CLK_ROOT, &val);
 		val = val & 0x3;
@@ -428,15 +445,13 @@ void init_clk_usdhc(u32 index)
 	case 0:
 		clock_enable(CCGR_USDHC1, 0);
 		clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
-				     CLK_ROOT_SOURCE_SEL(1) |
-				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+				     CLK_ROOT_SOURCE_SEL(1));
 		clock_enable(CCGR_USDHC1, 1);
 		return;
 	case 1:
 		clock_enable(CCGR_USDHC2, 0);
 		clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
-				     CLK_ROOT_SOURCE_SEL(1) |
-				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+				     CLK_ROOT_SOURCE_SEL(1));
 		clock_enable(CCGR_USDHC2, 1);
 		return;
 	default:
@@ -639,7 +654,7 @@ void dram_pll_init(ulong pll_val)
 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 {
 	void __iomem *pll_cfg0, __iomem *pll_cfg1;
-	u32 val_cfg0, val_cfg1;
+	u32 val_cfg0, val_cfg1, divq;
 	int ret;
 
 	switch (pll) {
@@ -647,14 +662,17 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 		pll_cfg0 = &ana_pll->arm_pll_cfg0;
 		pll_cfg1 = &ana_pll->arm_pll_cfg1;
 
-		if (val == FRAC_PLL_OUT_1000M)
+		if (val == FRAC_PLL_OUT_1000M) {
 			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
-		else
+			divq = 0;
+		} else {
 			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
+			divq = 1;
+		}
 		val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
 			FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
 			FRAC_PLL_REFCLK_DIV_VAL(4) |
-			FRAC_PLL_OUTPUT_DIV_VAL(0);
+			FRAC_PLL_OUTPUT_DIV_VAL(divq);
 		break;
 	default:
 		return -EINVAL;
@@ -690,17 +708,14 @@ int clock_init(void)
 	 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
 	 */
 	grade = get_cpu_temp_grade(NULL, NULL);
-	if (!grade) {
+	if (!grade)
 		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
-		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
-			     CLK_ROOT_SOURCE_SEL(1) |
-			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
-	} else {
-		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
-		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
-			     CLK_ROOT_SOURCE_SEL(1) |
-			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
-	}
+	else
+		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
+
+	/* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
+	clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
+
 	/*
 	 * According to ANAMIX SPEC
 	 * sys pll1 fixed at 800MHz
@@ -747,6 +762,8 @@ static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 
 	freq = decode_frac_pll(ARM_PLL_CLK);
 	printf("ARM_PLL    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(DRAM_PLL1_CLK);
+	printf("DRAM_PLL    %8d MHz\n", freq / 1000000);
 	freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
 	printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
 	freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 8b7a4dad65..b5ed27a923 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -472,33 +472,111 @@ static struct clk_root_map root_array[] = {
 	 {DRAM_PLL1_CLK}
 	},
 	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
-	 {DRAM_PLL1_CLK}
+	 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
 	},
 };
-#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
+#elif defined(CONFIG_IMX8MM)
 static struct clk_root_map root_array[] = {
 	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
 	},
+	{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+	},
+	{GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
 	{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 	},
+	{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_4}
+	},
+	{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_3}
+	},
+	{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  EXT_CLK_2, EXT_CLK_3}
+	},
+	{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
 	{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
 	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
 	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 	},
-#ifdef CONFIG_IMX8MM
 	{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
 	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
 	  SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
 	  SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 	},
-#endif
+	{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
 	{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@@ -509,6 +587,146 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 	},
+	{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+	 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+	},
+	{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  VIDEO_PLL_CLK}
+	},
+	{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+	 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+	},
+	{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
 	{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
@@ -529,19 +747,546 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 	},
+	{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
 	{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 	},
+	{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+	},
 	{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 	},
+	{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+	 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+	  SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+	},
+	{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+	},
+	{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+	 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+	  EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+	},
+	{VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
 	{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 	 {DRAM_PLL1_CLK}
 	},
+	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+	 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
+	},
+};
+#elif defined(CONFIG_IMX8MN)
+static struct clk_root_map root_array[] = {
+	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+	},
+	{ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+	},
+	{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_4}
+	},
+	{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_3}
+	},
+	{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+	},
+	{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+	},
+	{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  VIDEO_PLL_CLK}
+	},
+	{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+	 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+	},
+	{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+	},
+	{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+	},
+	{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+	 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+	  SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+	},
+	{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+	},
+	{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+	},
+	{SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+	 {DRAM_PLL1_CLK}
+	},
+	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+	 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
+	},
 };
 #elif defined(CONFIG_IMX8MP)
 static struct clk_root_map root_array[] = {
@@ -580,6 +1325,26 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 	},
+	{MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+	  AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
+	},
+	{MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+	  AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
+	},
+	{HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+	  AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
+	},
+	{HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
+	  AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
+	},
 	{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
 	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
@@ -605,6 +1370,11 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
 	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 	},
+	{MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
 	{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
@@ -615,11 +1385,6 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 	},
-	{MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6,
-	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
-	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
-	  SYSTEM_PLL1_133M_CLK}
-	},
 	{I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
 	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
@@ -798,11 +1563,36 @@ static struct clk_root_map root_array[] = {
 	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
 	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
 	},
+	{HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
+	  SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
 	{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
 	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 	},
+	{MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
 	{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
 	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
@@ -812,7 +1602,7 @@ static struct clk_root_map root_array[] = {
 	 {DRAM_PLL1_CLK}
 	},
 	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
-	 {DRAM_PLL1_CLK}
+	 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
 	},
 };
 #endif
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7fcbd53f30..89229da3b6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -165,7 +165,13 @@ static u32 get_cpu_variant_type(u32 type)
 
 	u32 value = readl(&fuse->tester4);
 
-	if (type == MXC_CPU_IMX8MM) {
+	if (type == MXC_CPU_IMX8MQ) {
+		if ((value & 0x3) == 0x2)
+			return MXC_CPU_IMX8MD;
+		else if (value & 0x200000)
+			return MXC_CPU_IMX8MQL;
+
+	} else if (type == MXC_CPU_IMX8MM) {
 		switch (value & 0x3) {
 		case 2:
 			if (value & 0x1c0000)
@@ -182,6 +188,23 @@ static u32 get_cpu_variant_type(u32 type)
 				return MXC_CPU_IMX8MML;
 			break;
 		}
+	} else if (type == MXC_CPU_IMX8MN) {
+		switch (value & 0x3) {
+		case 2:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNDL;
+			else
+				return MXC_CPU_IMX8MND;
+		case 3:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNSL;
+			else
+				return MXC_CPU_IMX8MNS;
+		default:
+			if (value & 0x1000000)
+				return MXC_CPU_IMX8MNL;
+			break;
+		}
 	}
 
 	return type;
@@ -202,7 +225,7 @@ u32 get_cpu_rev(void)
 		return (MXC_CPU_IMX8MP << 12) | reg;
 	} else if (major_low == 0x42) {
 		/* iMX8MN */
-		return (MXC_CPU_IMX8MN << 12) | reg;
+		type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 	} else if (major_low == 0x41) {
 		type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 	} else {
@@ -226,6 +249,8 @@ u32 get_cpu_rev(void)
 				}
 			}
 		}
+
+		type = get_cpu_variant_type(type);
 	}
 
 	return (type << 12) | reg;
@@ -364,16 +389,18 @@ int ft_system_setup(void *blob, bd_t *bd)
 			if (nodeoff < 0)
 				continue; /* Not found, skip it */
 
-			printf("Found %s node\n", nodes_path[i]);
+			debug("Found %s node\n", nodes_path[i]);
 
 			rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
+			if (rc == -FDT_ERR_NOTFOUND)
+				continue;
 			if (rc) {
 				printf("Unable to update property %s:%s, err=%s\n",
 				       nodes_path[i], "status", fdt_strerror(rc));
 				return rc;
 			}
 
-			printf("Remove %s:%s\n", nodes_path[i],
+			debug("Remove %s:%s\n", nodes_path[i],
 			       "cpu-idle-states");
 		}
 	}
@@ -382,21 +409,42 @@ int ft_system_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
+#if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(ulong addr)
 {
-       struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-       if (!addr)
-	       wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+	/* Clear WDA to trigger WDOG_B immediately */
+	writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
 
-       /* Clear WDA to trigger WDOG_B immediately */
-       writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+	while (1) {
+		/*
+		 * spin for .5 seconds before reset
+		 */
+	}
+}
+#endif
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+static void acquire_buildinfo(void)
+{
+	u64 atf_commit = 0;
+
+	/* Get ARM Trusted Firmware commit id */
+	atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
+				  IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
+	if (atf_commit == 0xffffffff) {
+		debug("ATF does not support build info\n");
+		atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
+	}
 
-       while (1) {
-               /*
-                * spin for .5 seconds before reset
-                */
-       }
+	printf("\n BuildInfo:\n  - ATF %s\n\n", (char *)&atf_commit);
+}
+
+int arch_misc_init(void)
+{
+	acquire_buildinfo();
+
+	return 0;
 }
 #endif
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 49bb3b928d..fd3fa04600 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -197,52 +197,35 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
 	case SD1_BOOT:
 	case SD2_BOOT:
 	case SD3_BOOT:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
-		return MMCSD_MODE_FS;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
+		if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+			return MMCSD_MODE_FS;
+		else
+			return MMCSD_MODE_RAW;
 	case MMC1_BOOT:
 	case MMC2_BOOT:
 	case MMC3_BOOT:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
-		return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
-		return MMCSD_MODE_EMMCBOOT;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
+		if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+			return MMCSD_MODE_FS;
+		else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+			return MMCSD_MODE_EMMCBOOT;
+		else
+			return MMCSD_MODE_RAW;
 	default:
 		puts("spl: ERROR:  unsupported device\n");
 		hang();
 	}
 #else
-/*
- * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used
- * unconditionally to decide about device to use for booting.
- * This is crucial for falcon boot mode, when board boots up (i.e. ROM
- * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot
- * mode is used to load Linux OS from eMMC partition.
- */
-#ifdef CONFIG_SPL_FORCE_MMC_BOOT
 	switch (boot_device) {
-#else
-	switch (spl_boot_device()) {
-#endif
 	/* for MMC return either RAW or FAT mode */
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
 	case BOOT_DEVICE_MMC2_2:
-#if defined(CONFIG_SPL_FS_FAT)
-		return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
-		return MMCSD_MODE_EMMCBOOT;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
+		if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+			return MMCSD_MODE_FS;
+		else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
+			return MMCSD_MODE_EMMCBOOT;
+		else
+			return MMCSD_MODE_RAW;
 	default:
 		puts("spl: ERROR:  unsupported device\n");
 		hang();
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 5d17f397cb..4d34622465 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -161,12 +161,3 @@ void board_init_f(ulong dummy)
 
 	board_init_r(NULL, 0);
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	puts ("resetting ...\n");
-
-	reset_cpu(WDOG1_BASE_ADDR);
-
-	return 0;
-}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 7aed14c52b..45417b2446 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -114,12 +114,3 @@ void board_init_f(ulong dummy)
 
 	board_init_r(NULL, 0);
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	puts("resetting ...\n");
-
-	reset_cpu(WDOG1_BASE_ADDR);
-
-	return 0;
-}
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 0b20668e2b..c5f640dc7b 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -139,7 +139,6 @@ void board_init_f(ulong dummy)
 
 	enable_tzc380();
 
-	/* Adjust pmic voltage to 1.0V for 800M */
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
 	power_init_board();
@@ -149,12 +148,3 @@ void board_init_f(ulong dummy)
 
 	board_init_r(NULL, 0);
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	puts("resetting ...\n");
-
-	reset_cpu(WDOG1_BASE_ADDR);
-
-	return 0;
-}
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index e442510f44..6ba6a52ebb 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -235,7 +235,6 @@ void board_init_f(ulong dummy)
 
 	enable_tzc380();
 
-	/* Adjust pmic voltage to 1.0V for 800M */
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
 	power_init_board();
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index b96f0da21e..93f0cd827c 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
 
@@ -111,6 +112,15 @@ int board_init(void)
 {
 	board_gpio_init();
 
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/imxrt1020-evk/README b/board/freescale/imxrt1020-evk/README
index 3da72fdad2..abee7ca5f3 100644
--- a/board/freescale/imxrt1020-evk/README
+++ b/board/freescale/imxrt1020-evk/README
@@ -11,11 +11,11 @@ This will generate the SPL image called SPL and the u-boot.img.
 
 - Flash the SPL image into the micro SD card:
 
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
 
 - Flash the u-boot.img image into the micro SD card:
 
-sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync
 
 - Jumper settings:
 
diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README
index f7e2894025..a7e68fa9b3 100644
--- a/board/freescale/imxrt1050-evk/README
+++ b/board/freescale/imxrt1050-evk/README
@@ -11,11 +11,11 @@ This will generate the SPL image called SPL and the u-boot.img.
 
 - Flash the SPL image into the micro SD card:
 
-sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
 
 - Flash the u-boot.img image into the micro SD card:
 
-sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128; sync
 
 - Jumper settings:
 
diff --git a/board/google/imx8mq_phanbell/Kconfig b/board/google/imx8mq_phanbell/Kconfig
new file mode 100644
index 0000000000..fba2e9ce67
--- /dev/null
+++ b/board/google/imx8mq_phanbell/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_PHANBELL
+
+config SYS_BOARD
+	default "imx8mq_phanbell"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_phanbell"
+
+endif
diff --git a/board/google/imx8mq_phanbell/MAINTAINERS b/board/google/imx8mq_phanbell/MAINTAINERS
new file mode 100644
index 0000000000..b233e6b57a
--- /dev/null
+++ b/board/google/imx8mq_phanbell/MAINTAINERS
@@ -0,0 +1,8 @@
+i.MX 8MQ PHANBELL BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+M:	Marco Franchi <marcofrk@gmail.com>
+M:	Alifer Moraes <alifer.wsdm@gmail.com>
+S:	Maintained
+F:	board/google/imx8mq_phanbell/
+F:	include/configs/imx8mq_phanbell.h
+F:	configs/imx8mq_phanbell_defconfig
diff --git a/board/google/imx8mq_phanbell/Makefile b/board/google/imx8mq_phanbell/Makefile
new file mode 100644
index 0000000000..d6427cf8e9
--- /dev/null
+++ b/board/google/imx8mq_phanbell/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 NXP
+#
+
+obj-y += imx8mq_phanbell.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o
+endif
diff --git a/board/google/imx8mq_phanbell/README b/board/google/imx8mq_phanbell/README
new file mode 100644
index 0000000000..88a136b32c
--- /dev/null
+++ b/board/google/imx8mq_phanbell/README
@@ -0,0 +1,37 @@
+U-Boot for Google's i.MX8MQ Phanbell board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.0.0
+$ make PLAT=imx8mq bl31
+$ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+=============================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+$ chmod +x firmware-imx-7.9.bin
+$ ./firmware-imx-7.9.bin
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make imx8mq_phanbell_defconfig
+$ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33
+
+Boot
+====
+Set Boot switch SW1: 1011 to boot from Micro SD.
diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c
new file mode 100644
index 0000000000..c0cc3e9b71
--- /dev/null
+++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
diff --git a/board/google/imx8mq_phanbell/lpddr4_timing_1g.c b/board/google/imx8mq_phanbell/lpddr4_timing_1g.c
new file mode 100644
index 0000000000..7800011a04
--- /dev/null
+++ b/board/google/imx8mq_phanbell/lpddr4_timing_1g.c
@@ -0,0 +1,1731 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400028, 0x0},
+	{0x3d400020, 0x203},
+	{0x3d400024, 0x3e800},
+	{0x3d400064, 0x610090},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x9e0000},
+	{0x3d4000dc, 0xd4002d},
+	{0x3d4000e0, 0x310008},
+	{0x3d4000e8, 0x66004a},
+	{0x3d4000ec, 0x16004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x60633},
+	{0x3d40010c, 0xc0c000},
+	{0x3d400110, 0xf04080f},
+	{0x3d400114, 0x2040c0c},
+	{0x3d400118, 0x1010007},
+	{0x3d40011c, 0x401},
+	{0x3d400130, 0x20600},
+	{0x3d400134, 0xc100002},
+	{0x3d400138, 0x96},
+	{0x3d400144, 0xa00050},
+	{0x3d400180, 0xc3200018},
+	{0x3d400184, 0x28061a8},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x497820a},
+	{0x3d400194, 0x80303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001b4, 0x170a},
+	{0x3d4001c0, 0x1},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x639},
+	{0x3d400108, 0x70e1617},
+	{0x3d400200, 0x1f},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0xf070707},
+	{0x3d402020, 0x1},
+	{0x3d402024, 0xd0c0},
+	{0x3d402050, 0x20d040},
+	{0x3d402064, 0x14001f},
+	{0x3d4020dc, 0x940009},
+	{0x3d4020e0, 0x310000},
+	{0x3d4020e8, 0x66004a},
+	{0x3d4020ec, 0x16004a},
+	{0x3d402100, 0xb070508},
+	{0x3d402104, 0x3040b},
+	{0x3d402108, 0x305090c},
+	{0x3d40210c, 0x505000},
+	{0x3d402110, 0x4040204},
+	{0x3d402114, 0x2030303},
+	{0x3d402118, 0x1010004},
+	{0x3d40211c, 0x301},
+	{0x3d402130, 0x20300},
+	{0x3d402134, 0xa100002},
+	{0x3d402138, 0x20},
+	{0x3d402144, 0x220011},
+	{0x3d402180, 0xc0a70006},
+	{0x3d402190, 0x3858202},
+	{0x3d402194, 0x80303},
+	{0x3d4021b4, 0x502},
+	{0x3d400244, 0x0},
+	{0x3d400250, 0x29001505},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x5900575b},
+	{0x3d400264, 0x90000096},
+	{0x3d40026c, 0x1000012c},
+	{0x3d400300, 0x16},
+	{0x3d400304, 0x0},
+	{0x3d40030c, 0x0},
+	{0x3d400320, 0x1},
+	{0x3d40036c, 0x11},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x10f3},
+	{0x3d400408, 0x72ff},
+	{0x3d400490, 0x1},
+	{0x3d400494, 0xe00},
+	{0x3d400498, 0x62ffff},
+	{0x3d40049c, 0xe00},
+	{0x3d4004a0, 0xffff},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x2},
+	{0x110a3, 0x3},
+	{0x110a4, 0x4},
+	{0x110a5, 0x5},
+	{0x110a6, 0x6},
+	{0x110a7, 0x7},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x2},
+	{0x120a3, 0x3},
+	{0x120a4, 0x4},
+	{0x120a5, 0x5},
+	{0x120a6, 0x6},
+	{0x120a7, 0x7},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x20110, 0x2},
+	{0x20111, 0x3},
+	{0x20112, 0x4},
+	{0x20113, 0x5},
+	{0x20114, 0x0},
+	{0x20115, 0x1},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x11205f, 0x1ff},
+	{0x11215f, 0x1ff},
+	{0x11305f, 0x1ff},
+	{0x11315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x19},
+	{0x1200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x20024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x120024, 0x1ab},
+	{0x2003a, 0x0},
+	{0x20056, 0x3},
+	{0x120056, 0xa},
+	{0x1004d, 0xe00},
+	{0x1014d, 0xe00},
+	{0x1104d, 0xe00},
+	{0x1114d, 0xe00},
+	{0x1204d, 0xe00},
+	{0x1214d, 0xe00},
+	{0x1304d, 0xe00},
+	{0x1314d, 0xe00},
+	{0x11004d, 0xe00},
+	{0x11014d, 0xe00},
+	{0x11104d, 0xe00},
+	{0x11114d, 0xe00},
+	{0x11204d, 0xe00},
+	{0x11214d, 0xe00},
+	{0x11304d, 0xe00},
+	{0x11314d, 0xe00},
+	{0x10049, 0xeba},
+	{0x10149, 0xeba},
+	{0x11049, 0xeba},
+	{0x11149, 0xeba},
+	{0x12049, 0xeba},
+	{0x12149, 0xeba},
+	{0x13049, 0xeba},
+	{0x13149, 0xeba},
+	{0x110049, 0xeba},
+	{0x110149, 0xeba},
+	{0x111049, 0xeba},
+	{0x111149, 0xeba},
+	{0x112049, 0xeba},
+	{0x112149, 0xeba},
+	{0x113049, 0xeba},
+	{0x113149, 0xeba},
+	{0x43, 0xe7},
+	{0x1043, 0xe7},
+	{0x2043, 0xe7},
+	{0x3043, 0xe7},
+	{0x4043, 0xe7},
+	{0x5043, 0xe7},
+	{0x6043, 0xe7},
+	{0x7043, 0xe7},
+	{0x8043, 0xe7},
+	{0x9043, 0xe7},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x320},
+	{0x120008, 0xa7},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x1200b2, 0xdc},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x112043, 0x5a1},
+	{0x112143, 0x5a1},
+	{0x113043, 0x5a1},
+	{0x113143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x1200fa, 0x1},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x200c7, 0x80},
+	{0x1200c7, 0x80},
+	{0x200ca, 0x106},
+	{0x1200ca, 0x106},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
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+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x29c},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400d, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x994},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0x9400},
+	{0x54033, 0x3109},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0x9400},
+	{0x54039, 0x3109},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xc80},
+	{0x54004, 0x2},
+	{0x54005, 0x2228},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x2dd4},
+	{0x5401a, 0x31},
+	{0x5401b, 0x4a66},
+	{0x5401c, 0x4a08},
+	{0x5401e, 0x16},
+	{0x5401f, 0x2dd4},
+	{0x54020, 0x31},
+	{0x54021, 0x4a66},
+	{0x54022, 0x4a08},
+	{0x54024, 0x16},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xd400},
+	{0x54033, 0x312d},
+	{0x54034, 0x6600},
+	{0x54035, 0x84a},
+	{0x54036, 0x4a},
+	{0x54037, 0x1600},
+	{0x54038, 0xd400},
+	{0x54039, 0x312d},
+	{0x5403a, 0x6600},
+	{0x5403b, 0x84a},
+	{0x5403c, 0x4a},
+	{0x5403d, 0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xf},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x630},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x630},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x630},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x630},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x630},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x630},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x630},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x630},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x630},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x630},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x630},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x630},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x630},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xa},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x2},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x900a4, 0x10},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x623},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x623},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x790},
+	{0x900a9, 0x11a},
+	{0x900aa, 0x8},
+	{0x900ab, 0x7aa},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x10},
+	{0x900ae, 0x7b2},
+	{0x900af, 0x2a},
+	{0x900b0, 0x0},
+	{0x900b1, 0x7c8},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x0},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xc},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x0},
+	{0x90169, 0x8},
+	{0x9016a, 0x8},
+	{0x9016b, 0x448},
+	{0x9016c, 0x109},
+	{0x9016d, 0xf},
+	{0x9016e, 0x7c0},
+	{0x9016f, 0x109},
+	{0x90170, 0x0},
+	{0x90171, 0xe8},
+	{0x90172, 0x109},
+	{0x90173, 0x47},
+	{0x90174, 0x630},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x618},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0xe0},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x7c8},
+	{0x9017e, 0x109},
+	{0x9017f, 0x8},
+	{0x90180, 0x8140},
+	{0x90181, 0x10c},
+	{0x90182, 0x0},
+	{0x90183, 0x1},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x4},
+	{0x90187, 0x8},
+	{0x90188, 0x8},
+	{0x90189, 0x7c8},
+	{0x9018a, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2a},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x14},
+	{0x12000c, 0x29},
+	{0x12000d, 0x1a1},
+	{0x12000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x60},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x2003a, 0x2},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c
new file mode 100644
index 0000000000..b6afdfc913
--- /dev/null
+++ b/board/google/imx8mq_phanbell/spl.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/sections.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(void)
+{
+	/* ddr init */
+	ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			usdhc_cfg[0].max_bus_width = 8;
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			usdhc_cfg[1].max_bus_width = 4;
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 3f85f1ac89..8c4a359c75 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -137,22 +137,79 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
-	/* control data pad skew - devaddr = 0x02, register = 0x04 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	int tmp;
+
+	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+	case PHY_ID_KSZ9131:
+		/* read rxc dll control - devaddr = 0x02, register = 0x4c */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+		/* read txc dll control - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on TXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x007d);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x7777);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0xdddd);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0007);
+		break;
+	case PHY_ID_KSZ9031:
+	default:
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+		break;
+	}
+
 	return 0;
 }
 
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index a5dc540820..dc5bd84f33 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -169,12 +169,3 @@ void board_init_f(ulong dummy)
 
 	board_init_r(NULL, 0);
 }
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	puts("resetting ...\n");
-
-	reset_cpu(WDOG1_BASE_ADDR);
-
-	return 0;
-}
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index cb9b4e3b0a..35866e096a 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <micrel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -37,14 +38,62 @@ static int setup_fec(void)
 
 int board_phy_config(struct phy_device *phydev)
 {
-	/* enable rgmii rxc skew and phy mode select to RGMII copper */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+	int tmp;
 
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+	case PHY_ID_KSZ9031:
+		/*
+		 * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
+		 * default. The MAC and the layout don't add a skew between
+		 * clock and data.
+		 * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
+		 * the TXC path to get the required clock skews.
+		 */
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0070);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x7777);
+		/* tx data pad skew - devaddr = 0x02, register = 0x06 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03f4);
+		break;
+	case PHY_ID_KSZ9131:
+	default:
+		/* read rxc dll control - devaddr = 0x2, register = 0x4c */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+		tmp = ksz9031_phy_extended_write(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+		/* read txc dll control - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable txdll bypass (enable 2ns skew delay on TXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_write(phydev, 0x02,
+					MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
+		break;
+	}
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ef5bf66696..9feadb5e43 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -663,15 +663,6 @@ config SPL_MMC_SUPPORT
 	  this option to build the drivers in drivers/mmc as part of an SPL
 	  build.
 
-config SPL_FORCE_MMC_BOOT
-	bool "Force SPL booting from MMC"
-	depends on SPL_MMC_SUPPORT
-	default n
-	help
-	  Force SPL to use MMC device for Linux kernel booting even when the
-	  SoC ROM recognized boot medium is not eMMC/SD. This is crucial for
-	  factory or 'falcon mode' booting.
-
 config SPL_MMC_TINY
 	bool "Tiny MMC framework in SPL"
 	depends on SPL_MMC_SUPPORT
diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig
index 388330afc4..628b3516a8 100644
--- a/configs/deneb_defconfig
+++ b/configs/deneb_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 4e10efd758..6241375c4c 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -39,7 +39,6 @@ CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_SAVEENV=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_FORCE_MMC_BOOT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
index 957875f782..3cae981a61 100644
--- a/configs/giedi_defconfig
+++ b/configs/giedi_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index e23d77d9f8..d4feb66162 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
 CONFIG_SPL_DMA=y
-CONFIG_SPL_FORCE_MMC_BOOT=y
 CONFIG_SPL_MMC_TINY=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index d988507bc3..9a72f46f27 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -30,6 +28,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_CMD_EXPORTENV is not set
@@ -82,5 +81,9 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+# CONFIG_WATCHDOG is not set
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index f7485ab272..bc6014d73a 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -32,6 +30,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_CMD_EXPORTENV is not set
@@ -76,5 +75,9 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+# CONFIG_WATCHDOG is not set
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index ce6b342c36..44b2935f69 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -81,4 +79,8 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+# CONFIG_WATCHDOG is not set
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 23fdb3f925..1504ecbbd6 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_ENV_SIZE=0x1000
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
new file mode 100644
index 0000000000..5be02a3382
--- /dev/null
+++ b/configs/imx8mq_phanbell_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_SD_BOOT=y
+# CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index f7debfbe7b..428c7c47cd 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig
index 301747a56c..35191447ae 100644
--- a/configs/imx8qm_rom7720_a1_4G_defconfig
+++ b/configs/imx8qm_rom7720_a1_4G_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 8a7e9ee9c7..4cc37f5de7 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -28,7 +26,6 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 590750e9b2..c852ad2623 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -38,6 +36,7 @@ CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SYS_PROMPT="Verdin iMX8MM # "
 # CONFIG_BOOTM_NETBSD is not set
 CONFIG_CMD_ASKENV=y
@@ -94,5 +93,9 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+# CONFIG_WATCHDOG is not set
+CONFIG_IMX_WATCHDOG=y
diff --git a/doc/imx/ahab/csf_examples/csf_enc_boot_image.txt b/doc/imx/ahab/csf_examples/csf_enc_boot_image.txt
new file mode 100644
index 0000000000..6c70db657b
--- /dev/null
+++ b/doc/imx/ahab/csf_examples/csf_enc_boot_image.txt
@@ -0,0 +1,27 @@
+[Header]
+Target = AHAB
+Version = 1.0
+
+[Install SRK]
+# SRK table generated by srktool
+File = "./release/crts/SRK_1_2_3_4_table.bin"
+# Public key certificate in PEM format
+Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem"
+# Index of the public key certificate within the SRK table (0 .. 3)
+Source index = 0
+# Type of SRK set (NXP or OEM)
+Source set = OEM
+# bitmask of the revoked SRKs
+Revocations = 0x0
+
+[Authenticate Data]
+# Binary to be signed generated by mkimage
+File = "flash.bin"
+# Offsets = Container header  Signature block (printed out by mkimage)
+Offsets   = 0x400             0x590
+
+[Install Secret Key]
+Key = "dek.bin"
+Key Length = 128
+#Key Identifier = 0x1234CAFE
+Image Indexes = 0xFFFFFFFE
diff --git a/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt
new file mode 100644
index 0000000000..dfea4c8277
--- /dev/null
+++ b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt
@@ -0,0 +1,293 @@
+         +=========================================================+
+         +      i.MX 8, i.MX 8X Encrypted Boot guide using AHAB    +
+         +=========================================================+
+
+1. AHAB Encrypted Boot process
+-------------------------------
+
+This document describes a step-by-step procedure on how to encrypt and sign a
+bootloader image for i.MX8/8x family devices. It is assumed that the reader
+is familiar with basic AHAB concepts and has already closed the device,
+step-by-step procedure can be found in mx8_mx8x_secure_boot.txt and
+mx8_mx8x_spl_secure_boot.txt guides.
+
+The steps described in this document were based in i.MX8QM device, the same
+concept can be applied to others processors in i.MX8/8X family devices.
+
+1.1 Understanding the encrypted image signature block
+------------------------------------------------------
+
+As described in mx8_mx8x_secure_boot.txt guide a single binary is used to boot
+the device. The imx-mkimage tool combines all the input images in a container
+structure, generating a flash.bin binary.
+
+AHAB is able to decrypt image containers by calling SECO authentication
+functions, the image must be encrypted by CST and the resulting DEK (Data
+Encryption Key) must be encapsulated and included into the container signature
+block:
+
+                +----------------------------+
+                |                            |  ^
+                |                            |  |
+                |      Container header      |  |
+                |                            |  |
+                |                            |  |
+                +---+------------------------+  |
+                | S | Signature block header |  | Signed
+                | i +------------------------+  |
+                | g |                        |  |
+                | n |                        |  |
+                | a |        SRK table       |  |
+                | t |                        |  |
+                | u |                        |  v
+                | r +------------------------+
+                | e |       Signature        |
+                |   +------------------------+
+                | B |                        |
+                | l |        SGK Key         |
+                | o | Certificate (optional) |
+                | c |                        |
+                | k +------------------------+
+                |   |        DEK Blob        |
+                +---+------------------------+
+
+1.1.1 Understanding and generating the DEK blob
+------------------------------------------------
+
+The encrypted boot image requires a DEK blob on each time AHAB is used to
+decrypt an image. The DEK blob is used as a security layer to wrap and store
+the DEK off-chip using the OTPMK which is unique per device.
+
+On i.MX8/8x devices the DEK blob is generated using the SECO API, the following
+funtion is available in U-Boot and can be executed through dek_blob command:
+
+- sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, sc_faddr_t load_addr,
+		       sc_faddr_t export_addr, uint16_t max_size)
+
+Details in API usage can be found in SCFW API guide [1].
+
+1.2 Enabling the encrypted boot support in U-Boot
+--------------------------------------------------
+
+For deploying an encrypted boot image additional U-Boot tools are needed,
+please be sure to have the following features enabled, this can be achieved
+by following one of the methods below:
+
+- Defconfig:
+
+  CONFIG_AHAB_BOOT=y
+  CONFIG_CMD_DEKBLOB=y
+  CONFIG_IMX_SECO_DEK_ENCAP=y
+  CONFIG_FAT_WRITE=y
+
+- Kconfig:
+
+  ARM architecture -> Support i.MX8 AHAB features
+  ARM architecture -> Support the 'dek_blob' command
+  File systems -> Enable FAT filesystem support-> Enable FAT filesystem
+  write support
+
+1.3 Enabling the encrypted boot support in CST
+-----------------------------------------------
+
+The encryption feature is not enabled by default in Code Signing tools (CST).
+The CST backend must be recompiled, execute the following commands to enable
+encryption support in CST:
+
+  $ sudo apt-get install libssl-dev openssl
+  $ cd <CST install directory>/code/back_end/src
+  $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c
+    -lfrontend -lcrypto
+  $ cp cst_encrypted ../../../linux64/bin/
+
+1.4 Preparing the image container
+----------------------------------
+
+The container generation is explained in and mx8_mx8x_secure_boot.txt and
+mx8_mx8x_spl_secure_boot.txt guides. This document is based in imx-mkimage
+flash target (2 containers in flash.bin).
+
+- Assembly flash.bin binary:
+
+  $ make SOC=<SoC Name> flash
+
+The mkimage log is used during the encrypted boot procedure to create the
+Command Sequence File (CSF):
+
+  CST: CONTAINER 0 offset: 0x400
+  CST: CONTAINER 0: Signature Block: offset is at 0x590
+  DONE.
+  Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET
+
+1.6 Creating the CSF description to encrypt the 2nd container
+--------------------------------------------------------------
+
+The csf_enc_boot_image.txt available under ahab/csf_examples/ can be used as
+example for encrypting the flash.bin binary, the main change is the Install
+Secret Key command that must be added after Authenticate Data command.
+
+  [Install Secret Key]
+  Key = "dek.bin"
+  Key Length = 128
+  #Key Identifier = 0x1234CAFE
+  Image Indexes = 0xFFFFFFFE
+
+By default all images are encrypted and image indexes parameter can be used
+to mask the images indexes that must be encrypted, on this example only the
+2nd container will be encrypted.
+
+Optionally users can provide a key identifier that must match the value
+provided during the blob generation, by default its value is zero.
+
+1.7 Encrypting the 2nd container
+---------------------------------
+
+The image is encrypted using the Code Signing Tool. The tool generates the
+encrypted image and a random dek.bin file.
+
+- Encrypt flash.bin binary:
+
+  $ ./cst_encrypted -i csf_enc_boot_image.txt -o enc_flash.bin
+   The DEK BLOB must be inserted at offset 0x7c0 (its expected size is 72 bytes)
+   CSF Processed successfully and signed image available in enc_boot_image.bin
+
+The output log will be used in a later step to insert the DEK blob into the
+signature block.
+
+1.8 Generating the DEK Blob
+----------------------------
+
+The DEK must be encapsulated into a CAAM blob so it can be included into the
+final encrypted binary. The U-Boot provides a tool called dek_blob which is
+calling the SECO blob encapsulation API.
+
+Copy the dek.bin in SDCard FAT partition and run the following commands from
+U-Boot prompt:
+
+  => mmc list
+     FSL_SDHC: 1 (SD)
+     FSL_SDHC: 2
+  => fatload mmc 1:1 0x80280000 dek.bin
+  => dek_blob 0x80280000 0x80280100 128
+  => fatwrite mmc 1:1 0x80280100 dek_blob.bin 0x48
+
+In host PC copy the generated dek_blob.bin to the CST directory.
+
+1.9 Assembling the encrypted image
+-----------------------------------
+
+The DEK blob generated in the step above have to be inserted into the container
+signature block.
+
+The CSF log is used to determine the DEK Blob offset:
+
+  The DEK BLOB must be inserted at offset 0x7c0 (its expected size is 72 bytes)
+  CSF Processed successfully and signed image available in enc_boot_image.bin
+
+- Insert DEK Blob into container signature block:
+
+  $ dd if=dek_blob.bin of=enc_flash.bin bs=1 seek=$((0x7c0)) conv=notrunc
+
+1.10 Flashing the encrypted boot image
+---------------------------------------
+
+The same offset is used for encrypted boot images, in case booting from
+eMMC/SDCard the offset is 32K.
+
+- Flash encrypted image in SDCard:
+
+  $ sudo dd if=enc_flash.bin of=/dev/sd<x> bs=1K seek=32 && sync
+
+2.0 Encrypting a standalone container
+--------------------------------------
+
+CST is also able to encrypt additional images containers, the steps documented
+in this section are based in OS container but can be also applied to SPL
+targets and 3rd containers.
+
+2.1 Creating the OS container
+------------------------------
+
+As explained in mx8_mx8x_secure_boot.txt guide the imx-mkimage tool is used to
+generate an image container for OS images, the mkimage log is used during the
+encrypted boot procedure to create the Command Sequence File (CSF).
+
+- Creating OS container:
+
+  $ make SOC=<SoC Name> flash_kernel
+   ...
+   CST: CONTAINER 0 offset: 0x0
+   CST: CONTAINER 0: Signature Block: offset is at 0x110
+
+2.2 Creating the CSF description file for standalone container
+---------------------------------------------------------------
+
+The Image Indexes parameter is used to mask the images that are encrypted by
+CST, as a single container is used for OS images the Image Indexes command can
+be commented or set to 0xFFFFFFFF.
+
+  [Install Secret Key]
+  Key = "dek_os.bin"
+  Key Length = 128
+  #Key Identifier = 0x1234CAFE
+  Image Indexes = 0xFFFFFFFF
+
+2.3 Encrypting the standalone container
+----------------------------------------
+
+As explained in section 1.7 the CST generates the encrypted image and a random
+dek.bin file.
+
+- Encrypt the standalone container:
+
+  $ ./cst_encrypted -i csf_linux_img.txt -o enc_flash_os.bin
+   The DEK BLOB must be inserted at offset 0x340 (its expected size is 72 bytes)
+   CSF Processed successfully and signed image available in enc_flash_os.bin
+
+The output log will be used in a later step to insert the DEK blob into the
+signature block.
+
+2.4 Generating the DEK Blob for standalone container
+----------------------------------------------------
+
+Similar to section 1.8 the DEK must be encapsulated into a CAAM blob so it can
+be included into the final encrypted binary.
+
+Copy the dek_os.bin in SDCard FAT partition and run the following commands from
+U-Boot prompt:
+
+  => mmc list
+     FSL_SDHC: 1 (SD)
+     FSL_SDHC: 2
+  => fatload mmc 1:1 0x80280000 dek_os.bin
+  => dek_blob 0x80280000 0x80280100 128
+  => fatwrite mmc 1:1 0x80280100 dek_blob_os.bin 0x48
+
+In host PC copy the generated dek_blob_os.bin to the CST directory.
+
+2.5 Assembling the encrypted image
+-----------------------------------
+
+The DEK blob generated in the step above have to be inserted into the container
+signature block.
+
+The CSF log is used to determine the DEK Blob offset:
+
+   The DEK BLOB must be inserted at offset 0x340 (its expected size is 72 bytes)
+   CSF Processed successfully and signed image available in enc_flash_os.bin
+
+- Insert DEK Blob into container signature block:
+
+  $ dd if=dek_blob_os.bin of=enc_flash_os.bin bs=1 seek=$((0x340)) conv=notrunc
+
+2.6 Copy encrypted image to SDCard
+-----------------------------------
+
+The encrypted container can be copied to SDCard FAT partition, please note
+that U-Boot requires signed and encrypted containers to be named as
+os_cntr_signed.bin.
+
+  $ sudo cp enc_flash_os.bin /media/UserID/Boot\ imx8/os_cntr_signed.bin
+
+References:
+[1] SCFW API guide: "System Controller Firmware API Reference Guide - Rev 1.5"
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 329f4580c5..8279e784fe 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,7 +255,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 	clk_dm(IMXRT1050_CLK_SEMC,
 	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
 	clk_dm(IMXRT1050_CLK_LCDIF,
-	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
 
 	struct clk *clk, *clk1;
 
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 3ad21c1ea0..3e38edbf5d 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -174,6 +174,28 @@ sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt)
 	return !!result;
 }
 
+int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	int size = sizeof(struct sc_rpc_msg_s);
+	struct sc_rpc_msg_s msg;
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 2U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = (u8)(PM_FUNC_RESOURCE_RESET);
+
+	RPC_U16(&msg, 0U) = (u16)(resource);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: resource:%d res:%d\n",
+		       __func__, resource, RPC_R8(&msg));
+
+	return ret;
+}
+
 /* PAD */
 int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val)
 {
@@ -200,6 +222,34 @@ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val)
 	return ret;
 }
 
+int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, u32 *val)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	int size = sizeof(struct sc_rpc_msg_s);
+	struct sc_rpc_msg_s msg;
+	int ret;
+
+	if (!dev)
+		hang();
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 2U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = (u8)(PAD_FUNC_GET);
+
+	RPC_U16(&msg, 0U) = (u16)(pad);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: pad:%d: res:%d\n",
+		       __func__, pad, RPC_R8(&msg));
+
+	if (val)
+		*val = (u32)RPC_U32(&msg, 0U);
+
+	return ret;
+}
+
 /* MISC */
 int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
 			sc_ctrl_t ctrl, u32 val)
@@ -948,3 +998,147 @@ int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 
 	return ret;
 }
+
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr,
+			u16 dst_size)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 4U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_GET_MP_KEY);
+
+	RPC_U32(&msg, 0U) = (u32)(dst_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = (u32)(dst_addr);
+	RPC_U16(&msg, 8U) = (u16)(dst_size);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s, dst_addr:0x%llx, res:%d\n",
+		       __func__, dst_addr, RPC_R8(&msg));
+
+	return ret;
+}
+
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size_m,
+			u8 lock)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 4U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_UPDATE_MPMR);
+
+	RPC_U32(&msg, 0U) = (u32)(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = (u32)(addr);
+	RPC_U8(&msg, 8U) = (u8)(size_m);
+	RPC_U8(&msg, 9U) = (u8)(lock);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s, addr:0x%llx, size_m:%x, lock:0x%x, res:%d\n",
+		       __func__, addr, size_m, lock, RPC_R8(&msg));
+	return ret;
+}
+
+int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+			u16 msg_size, sc_faddr_t dst_addr,
+			u16 dst_size)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 6U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_GET_MP_SIGN);
+
+	RPC_U32(&msg, 0U) = (u32)(msg_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = (u32)(msg_addr);
+	RPC_U32(&msg, 8U) = (u32)(dst_addr >> 32ULL);
+	RPC_U32(&msg, 12U) = (u32)(dst_addr);
+	RPC_U16(&msg, 16U) = (u16)(msg_size);
+	RPC_U16(&msg, 18U) = (u16)(dst_size);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s, msg_addr:0x%llx, msg_size:%x, dst_addr:0x%llx,"
+		       "dst_size:%x, res:%d\n", __func__, msg_addr, msg_size,
+		       dst_addr, dst_size, RPC_R8(&msg));
+
+	return ret;
+}
+
+int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
+			  u32 *data0, u32 *data1, u32 *data2, u32 *data3,
+			  u32 *data4, u8 size)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int msg_size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 7U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_SECVIO_CONFIG);
+
+	RPC_U32(&msg, 0U) = (u32)(*data0);
+	RPC_U32(&msg, 4U) = (u32)(*data1);
+	RPC_U32(&msg, 8U) = (u32)(*data2);
+	RPC_U32(&msg, 12U) = (u32)(*data3);
+	RPC_U32(&msg, 16U) = (u32)(*data4);
+	RPC_U8(&msg, 20U) = (u8)(id);
+	RPC_U8(&msg, 21U) = (u8)(access);
+	RPC_U8(&msg, 22U) = (u8)(size);
+
+	ret = misc_call(dev, SC_FALSE, &msg, msg_size, &msg, msg_size);
+	if (ret)
+		printf("%s, id:0x%x, access:%x, res:%d\n",
+		       __func__, id, access, RPC_R8(&msg));
+
+	*data0 = (u32)RPC_U32(&msg, 0U);
+	*data1 = (u32)RPC_U32(&msg, 4U);
+	*data2 = (u32)RPC_U32(&msg, 8U);
+	*data3 = (u32)RPC_U32(&msg, 12U);
+	*data4 = (u32)RPC_U32(&msg, 16U);
+
+	return ret;
+}
+
+int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 3U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_SECVIO_DGO_CONFIG);
+
+	RPC_U32(&msg, 0U) = (u32)(*data);
+	RPC_U8(&msg, 4U) = (u8)(id);
+	RPC_U8(&msg, 5U) = (u8)(access);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s, id:0x%x, access:%x, res:%d\n",
+		       __func__, id, access, RPC_R8(&msg));
+
+	if (data)
+		*data = RPC_U32(&msg, 0U);
+
+	return ret;
+}
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index bc5b63d788..345d37be4e 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -503,6 +503,16 @@ static int fec_open(struct eth_device *edev)
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 	       &fec->eth->ecntrl);
 
+#ifdef FEC_ENET_ENABLE_TXC_DELAY
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
+	       &fec->eth->ecntrl);
+#endif
+
+#ifdef FEC_ENET_ENABLE_RXC_DELAY
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
+	       &fec->eth->ecntrl);
+#endif
+
 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	udelay(100);
 
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 159aec8967..3c8fdda263 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -188,6 +188,8 @@ struct ethernet_regs {
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
 #define FEC_ECNTRL_SPEED		0x00000020
 #define FEC_ECNTRL_DBSWAP		0x00000100
+#define FEC_ECNTRL_TXC_DLY		0x00010000	/* TXC delayed */
+#define FEC_ECNTRL_RXC_DLY		0x00020000	/* RXC delayed */
 
 #define FEC_X_WMRK_STRFWD		0x00000100
 
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index 0105fc5af1..f0032e8ce1 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -383,8 +383,8 @@ static int ksz9031_config(struct phy_device *phydev)
 
 static struct phy_driver ksz9031_driver = {
 	.name = "Micrel ksz9031",
-	.uid  = 0x221620,
-	.mask = 0xfffff0,
+	.uid  = PHY_ID_KSZ9031,
+	.mask = MII_KSZ9x31_SILICON_REV_MASK,
 	.features = PHY_GBIT_FEATURES,
 	.config   = &ksz9031_config,
 	.startup  = &ksz90xx_startup,
@@ -393,9 +393,67 @@ static struct phy_driver ksz9031_driver = {
 	.readext = &ksz9031_phy_extread,
 };
 
+/*
+ * KSZ9131
+ */
+static int ksz9131_config(struct phy_device *phydev)
+{
+	/* TBD: Implement Skew values for dts */
+
+	/* add an option to disable the gigabit feature of this PHY */
+	if (env_get("disable_giga")) {
+		unsigned features;
+		unsigned bmcr;
+
+		/* disable speed 1000 in features supported by the PHY */
+		features = phydev->drv->features;
+		features &= ~(SUPPORTED_1000baseT_Half |
+				SUPPORTED_1000baseT_Full);
+		phydev->advertising = phydev->supported = features;
+
+		/* disable speed 1000 in Basic Control Register */
+		bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+		bmcr &= ~(1 << 6);
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
+
+		/* disable speed 1000 in 1000Base-T Control Register */
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
+
+		/* start autoneg */
+		genphy_config_aneg(phydev);
+		genphy_restart_aneg(phydev);
+
+		return 0;
+	}
+
+	return genphy_config(phydev);
+}
+
+static struct phy_driver ksz9131_driver = {
+	.name = "Micrel ksz9031",
+	.uid  = PHY_ID_KSZ9131,
+	.mask = MII_KSZ9x31_SILICON_REV_MASK,
+	.features = PHY_GBIT_FEATURES,
+	.config   = &ksz9131_config,
+	.startup  = &ksz90xx_startup,
+	.shutdown = &genphy_shutdown,
+	.writeext = &ksz9031_phy_extwrite,
+	.readext = &ksz9031_phy_extread,
+};
+
+int ksz9xx1_phy_get_id(struct phy_device *phydev)
+{
+	unsigned int phyid;
+
+	get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phyid);
+
+	return phyid;
+}
+
 int phy_micrel_ksz90x1_init(void)
 {
 	phy_register(&ksz9021_driver);
 	phy_register(&ksz9031_driver);
+	phy_register(&ksz9131_driver);
 	return 0;
 }
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 8a5a61c9fb..12d00b4689 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -77,6 +77,12 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 		dev_err(dev, "Failed to set mxs clk: %d\n", ret);
 		return;
 	}
+
+	ret = clk_enable(&per_clk);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+		return;
+	}
 #else
 	/* Kick in the LCDIF clock */
 	mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index bea035c3e2..4003715733 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -24,6 +24,7 @@
 
 /* Networking */
 #define FEC_QUIRK_ENET_MAC
+#define FEC_ENET_ENABLE_TXC_DELAY
 
 #define CONFIG_TFTP_TSIZE
 
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
new file mode 100644
index 0000000000..4fa48c0578
--- /dev/null
+++ b/include/configs/imx8mq_phanbell.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX8M_PHANBELL_H
+#define __IMX8M_PHANBELL_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SPL_MAX_SIZE		(172 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR      0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000	/* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE			0x30BE0000
+
+#define CONFIG_PHYLIB
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffff\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=imx8mq-phanbell.dtb\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x40000000 /* 1GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					(PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_PMIC
+#endif
+
+#endif
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 984cf611f4..dc5e818443 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -143,12 +143,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_SIZE		SZ_32M
-#define FSL_QSPI_FLASH_NUM		2
-#endif
-
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV		0  /*USDHC3*/
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 86007a2d36..3bff496bad 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -173,17 +173,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_LE
-#define CONFIG_SYS_FSL_QSPI_AHB
-#ifdef CONFIG_MX6SX_SABRESD_REVA
-#define FSL_QSPI_FLASH_SIZE		SZ_16M
-#else
-#define FSL_QSPI_FLASH_SIZE		SZ_32M
-#endif
-#define FSL_QSPI_FLASH_NUM		2
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_MXS
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index a30d2c0879..1bdd577940 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -157,12 +157,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM		1
-#define FSL_QSPI_FLASH_SIZE		SZ_32M
-#endif
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index af335bcfff..3d42d26aa4 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -160,12 +160,6 @@
 
 #define CONFIG_SOFT_SPI
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM		1
-#define FSL_QSPI_FLASH_SIZE		SZ_32M
-#endif
-
 #ifdef CONFIG_CMD_NET
 #define CONFIG_FEC_ENET_DEV		1
 #if (CONFIG_FEC_ENET_DEV == 0)
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index e7d35ed648..fa59748776 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -154,12 +154,4 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM		1
-#define FSL_QSPI_FLASH_SIZE		SZ_64M
-#define QSPI0_BASE_ADDR			QSPI1_IPS_BASE_ADDR
-#define QSPI0_AMBA_BASE			QSPI0_ARB_BASE_ADDR
-#endif
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 72f8d08a66..d4d6ad2143 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -26,13 +26,6 @@
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-/* QSPI Configs*/
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
-#define FSL_QSPI_FLASH_NUM		2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
 
 #define CONFIG_LOADADDR			0x82000000
 
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 3ab3231943..d52a5a7e83 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -43,14 +43,6 @@
 #define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
 
-/* QSPI Configs*/
-
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE		(1 << 24)
-#define FSL_QSPI_FLASH_NUM		2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h b/include/dt-bindings/pinctrl/pins-imxrt1020.h
index c6bacb7378..b3a833bde2 100644
--- a/include/dt-bindings/pinctrl/pins-imxrt1020.h
+++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
@@ -7,8 +7,6 @@
 #ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
 #define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
 
-/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
-
 #define IMX_PAD_SION	0x40000000
 
 /*
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 139ff61b8a..26dbe0421a 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -7,7 +7,10 @@
 #define _IMX_SIP_H_
 
 #define IMX_SIP_GPC		0xC2000000
-#define  IMX_SIP_GPC_PM_DOMAIN	0x03
+#define IMX_SIP_GPC_PM_DOMAIN	0x03
+
+#define IMX_SIP_BUILDINFO			0xC2000003
+#define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 #define IMX_SIP_SRC		0xC2000005
 #define IMX_SIP_SRC_M4_START	0x00
diff --git a/include/micrel.h b/include/micrel.h
index 3e6b5312d8..a2593c5b10 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -23,6 +23,16 @@
 #define MII_KSZ9031_FLP_BURST_TX_LO		0x3
 #define MII_KSZ9031_FLP_BURST_TX_HI		0x4
 
+#define MII_KSZ9x31_SILICON_REV_MASK		0xfffff0
+
+#define MII_KSZ9131_RXTXDLL_BYPASS		BIT(12)
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL	0x4c
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL	0x4d
+
+#define PHY_ID_KSZ9031				0x00221620
+#define PHY_ID_KSZ9131				0x00221640
+
+
 /* Registers */
 #define MMD_ACCESS_CONTROL	0xd
 #define MMD_ACCESS_REG_DATA	0xe
@@ -35,5 +45,6 @@ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
 			       int regnum, u16 mode, u16 val);
 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 			      int regnum, u16 mode);
+int ksz9xx1_phy_get_id(struct phy_device *phydev);
 
 #endif