diff options
| author | Yuantian Tang <andy.tang@nxp.com> | 2020-06-10 16:13:50 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 14:16:28 +0530 |
| commit | c8f8830e0bae17f1163de6d413d0553ba5a67416 (patch) | |
| tree | 7df41463c9e85fed8b32e84e807be848b6aaa5bf | |
| parent | cb1de6067aae8bd3dc8161db0d92f19a4e60942a (diff) | |
| download | u-boot-c8f8830e0bae17f1163de6d413d0553ba5a67416.tar.gz | |
armv8: ls1028ardb: add xspi parameter to qixis command
Add xspi boot source to qixis command to let the soc boot from
flex-nor flash chip.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | board/freescale/common/qixis.c | 13 | ||||
| -rw-r--r-- | include/configs/ls1028ardb.h | 4 |
2 files changed, 15 insertions, 2 deletions
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 591203132f..1696c24e27 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -324,6 +324,19 @@ static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, #else printf("Not implemented\n"); #endif + } else if (strcmp(argv[1], "xspi") == 0) { +#ifdef QIXIS_LBMAP_XSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_XSPI); + set_rcw_src(QIXIS_RCW_SRC_XSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 0745011326..e6f38f5d00 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -38,10 +38,10 @@ #define QIXIS_LBMAP_ALTBANK 0x00 #define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_LBMAP_XSPI 0x00 #define QIXIS_RCW_SRC_SD 0xf8 #define QIXIS_RCW_SRC_EMMC 0xf9 -#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RCW_SRC_XSPI 0xff #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 #define QIXIS_RCFG_CTL_RECONFIG_START 0x11 |