diff options
| author | Zhao Qiang <B45475@freescale.com> | 2015-03-26 16:13:09 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:24:16 -0700 |
| commit | 5066e62847bddf6030262ade2aa3e7bcdc930037 (patch) | |
| tree | 92d5aa42673b6b529453f3cec05fb8799bf9b039 | |
| parent | 373762c34cd33b4a445b758090daaa87ccfa3fc6 (diff) | |
| download | u-boot-5066e62847bddf6030262ade2aa3e7bcdc930037.tar.gz | |
T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 15 | ||||
| -rw-r--r-- | include/configs/T208xQDS.h | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b07573f..152045ed93 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; +#ifdef CONFIG_FSL_PCIE_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + } +#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 046aa48baa..6adcb22521 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -575,6 +575,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |