diff options
| author | Dinesh Maniyam <dinesh.maniyam@intel.com> | 2022-10-14 10:43:38 +0800 |
|---|---|---|
| committer | dineshmaniyam <99864906+dineshmaniyam@users.noreply.github.com> | 2022-10-21 14:37:55 +0800 |
| commit | 1a7634ebead841ce94dd36da7cd93f2b78c67032 (patch) | |
| tree | 220445463d4f07470723eac4c5fec95db3ff7b55 | |
| parent | 4d1a7e0ee3f65b41e9078cb79f0291f760756e21 (diff) | |
| download | u-boot-socfpga-1a7634ebead841ce94dd36da7cd93f2b78c67032.tar.gz | |
altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)rel_socfpga_v2022.07_RC_22.11.02_pr
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
| -rw-r--r-- | drivers/clk/altera/clk-mem-n5x.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem-n5x.h index 7b687012e8..57362c0b37 100644 --- a/drivers/clk/altera/clk-mem-n5x.h +++ b/drivers/clk/altera/clk-mem-n5x.h @@ -77,7 +77,7 @@ #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ (MEMCLKMGR_EXTCNTRST_C0CNTRST) |