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authorhuijie.huang <huijie.huang@amlogic.com>2019-04-12 11:35:35 +0800
committerDongjin Kim <tobetter@gmail.com>2019-05-16 13:20:34 +0900
commit74b81be38f6383d5c25b41ce3f96f4c6ebec7e17 (patch)
treea1f0cf540726bbfda5d37b499318cd97f54200e7
parent7d5aae030cb8faa2ae6c0a61bd86cd5f2ddf2209 (diff)
downloadu-boot-odroid-c1-74b81be38f6383d5c25b41ce3f96f4c6ebec7e17.tar.gz
uboot: support sm1 socket board [1/2]
PD#SWPL-7014 Problem: sm1 socket bring up, support multi-dts Solution: sm1 socket bring up Verify: s905x3/s905x2 socket board Change-Id: Id6b60d2957d22587d70de1320b6c8787e5a48ad9 Signed-off-by: huijie.huang <huijie.huang@amlogic.com>
-rw-r--r--board/amlogic/configs/g12a_skt_v1.h3
-rw-r--r--board/amlogic/g12a_skt_v1/g12a_skt_v1.c57
2 files changed, 42 insertions, 18 deletions
diff --git a/board/amlogic/configs/g12a_skt_v1.h b/board/amlogic/configs/g12a_skt_v1.h
index 948058f798..3c989f3dfa 100644
--- a/board/amlogic/configs/g12a_skt_v1.h
+++ b/board/amlogic/configs/g12a_skt_v1.h
@@ -551,7 +551,8 @@
#define CONFIG_CMD_CPU_TEMP 1
#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
#define CONFIG_CMD_LOADB 1
-//#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_MULTI_DTB 1
/* debug mode defines */
//#define CONFIG_DEBUG_MODE 1
diff --git a/board/amlogic/g12a_skt_v1/g12a_skt_v1.c b/board/amlogic/g12a_skt_v1/g12a_skt_v1.c
index 5100553bde..341d2053e7 100644
--- a/board/amlogic/g12a_skt_v1/g12a_skt_v1.c
+++ b/board/amlogic/g12a_skt_v1/g12a_skt_v1.c
@@ -788,25 +788,48 @@ int checkhw(char * name)
* hwid = 1 p321 v1
* hwid = 2 p321 v2
*/
- unsigned int hwid = 1;
+ unsigned int ddr_size=0;
char loc_name[64] = {0};
+ int i;
+ cpu_id_t cpu_id=get_cpu_id();
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ if (MESON_CPU_MAJOR_ID_SM1 == cpu_id.family_id) {
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "sm1_skt_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "sm1_skt_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "sm1_skt_512m\0");
+ break;
+ default:
+ strcpy(loc_name, "sm1_skt_unsupport");
+ break;
+ }
+ }
+ else {
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "g12a_skt_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "g12a_skt_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "g12a_skt_512m\0");
+ break;
+ default:
+ strcpy(loc_name, "g12a_skt_unsupport");
+ break;
+ }
}
strcpy(name, loc_name);
setenv("aml_dt", loc_name);