diff options
| author | Evoke Zhang <evoke.zhang@amlogic.com> | 2019-05-14 12:03:23 +0800 |
|---|---|---|
| committer | Dongjin Kim <tobetter@gmail.com> | 2020-02-13 17:13:40 +0900 |
| commit | 75831ce548f14f1a5418fb24dc37dddc0f8b7ae9 (patch) | |
| tree | b4732dbfb011c71807b986b4e97d49219d6f2f87 | |
| parent | 0b4b606f35f22e7723b23cd77cd667bd8e8ee841 (diff) | |
| download | u-boot-odroid-c1-75831ce548f14f1a5418fb24dc37dddc0f8b7ae9.tar.gz | |
vout: support vout2 command for viu2 display [1/1]
PD#TV-5428
Problem:
need viu2 display support
Solution:
add vout2 management
you can use "vout2 output ${outputmode}" to enable vout2 display
Verify:
x301
Change-Id: Id47e430453ebdf7c32f41d271d6e926fd5cf0f6b
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
35 files changed, 537 insertions, 319 deletions
diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c index ec2ac574f6..4d4209c661 100644 --- a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c @@ -65,20 +65,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while(0); -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -345,7 +331,6 @@ void set_hdmitx_clk(enum hdmi_vic vic) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); set_hpll_od1(p_enc[j].od1); diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c index 8be50642b5..cbe14fb6ed 100644 --- a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -406,7 +407,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -415,8 +416,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c index 1de1ea117b..04a4353b1f 100644 --- a/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c index 25b331fc48..c5bf713ce1 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c @@ -70,19 +70,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} static void set_hdmitx_sys_clk(void) { @@ -1124,7 +1111,6 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev) } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev); if (!getenv("sspll_dis")) diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c index 776c48b61e..565c8d35ea 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -502,7 +503,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -511,8 +512,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c index 9d7e1a6ed6..a911cce90d 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_tvenc.c @@ -58,7 +58,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_DE_V_END_EVEN, 0x2E9,}, {P_ENCP_DE_V_BEGIN_ODD, 0x0,}, {P_ENCP_DE_V_END_ODD, 0x0,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -98,7 +97,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_DE_V_END_EVEN, 0x2E9,}, {P_ENCP_DE_V_BEGIN_ODD, 0x0,}, {P_ENCP_DE_V_END_ODD, 0x0,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -130,7 +128,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -167,7 +164,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -204,7 +200,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -241,7 +236,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -281,7 +275,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0018}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -317,7 +310,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0018}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -351,7 +343,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -391,7 +382,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -431,7 +421,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -464,7 +453,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -497,7 +485,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -530,7 +517,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -563,7 +549,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -586,7 +571,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -609,7 +593,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -1006,6 +989,30 @@ static const struct reg_t tvregs_vesa_2560x1080p60hz[] = { {MREG_END_MARKER, 0}, }; +static const struct reg_t tvregs_vesa_1440x2560p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x623,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0xA23,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x44,}, + {P_ENCP_VIDEO_HAVON_END, 0x5E3,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0xA13,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x4,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + struct vic_tvregs_set { enum hdmi_vic vic; const struct reg_t *reg_setting; diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c index 25b331fc48..47da9e9e13 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c @@ -70,20 +70,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -1124,7 +1110,6 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev) } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev); if (!getenv("sspll_dis")) diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c index 776c48b61e..565c8d35ea 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -502,7 +503,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -511,8 +512,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c index 9d7e1a6ed6..9434bc4d18 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_tvenc.c @@ -58,7 +58,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_DE_V_END_EVEN, 0x2E9,}, {P_ENCP_DE_V_BEGIN_ODD, 0x0,}, {P_ENCP_DE_V_END_ODD, 0x0,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -98,7 +97,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_DE_V_END_EVEN, 0x2E9,}, {P_ENCP_DE_V_BEGIN_ODD, 0x0,}, {P_ENCP_DE_V_END_ODD, 0x0,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -130,7 +128,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -167,7 +164,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -204,7 +200,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -241,7 +236,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -281,7 +275,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0018}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -317,7 +310,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0018}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -351,7 +343,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -391,7 +382,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -431,7 +421,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -464,7 +453,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -497,7 +485,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -530,7 +517,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -563,7 +549,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -586,7 +571,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -609,7 +593,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c index 84582d6e27..7590a5f9e0 100644 --- a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c @@ -68,20 +68,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -372,7 +358,6 @@ void set_hdmitx_clk(enum hdmi_vic vic) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); set_hpll_od1(p_enc[j].od1); diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c index 25fe4119d2..3d1dacf4ac 100644 --- a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include <amlogic/sound.h> #include "hdmitx_reg.h" @@ -414,7 +415,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -423,8 +424,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c index 9c4dad7d38..ff6bc1ac8a 100644 --- a/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/gxb/hdmitx20/hdmitx_tvenc.c @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c index c4169775c6..da6964d482 100644 --- a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c @@ -70,20 +70,6 @@ static uint32_t frac_rate; printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -947,7 +933,6 @@ static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); if (!getenv("sspll_dis")) diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c index f0702ca1c0..6e8c4f5061 100644 --- a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include <amlogic/sound.h> #include "hdmitx_reg.h" @@ -430,7 +431,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -439,8 +440,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c index 3572484923..183194812b 100644 --- a/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/gxl/hdmitx20/hdmitx_tvenc.c @@ -51,7 +51,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -87,7 +86,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -123,7 +121,6 @@ static const struct reg_t tvregs_720p_100hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -156,7 +153,6 @@ static const struct reg_t tvregs_720p_120hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -188,7 +184,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -225,7 +220,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -262,7 +256,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -299,7 +292,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -339,7 +331,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -375,7 +366,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -409,7 +399,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -449,7 +438,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -489,7 +477,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -522,7 +509,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -555,7 +541,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -588,7 +573,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -621,7 +605,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -644,7 +627,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -667,7 +649,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -692,7 +673,6 @@ static const struct reg_t tvregs_vesa_640x480p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x2,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -717,7 +697,6 @@ static const struct reg_t tvregs_vesa_800x600p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -742,7 +721,6 @@ static const struct reg_t tvregs_vesa_800x480p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0}, {P_ENCP_VIDEO_VSO_ELINE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -765,7 +743,6 @@ static const struct reg_t tvregs_vesa_852x480p60hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -788,7 +765,6 @@ static const struct reg_t tvregs_vesa_854x480p60hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -813,7 +789,6 @@ static const struct reg_t tvregs_vesa_1024x600p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -838,7 +813,6 @@ static const struct reg_t tvregs_vesa_1024x768p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -863,7 +837,6 @@ static const struct reg_t tvregs_vesa_1152x864p75hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -889,7 +862,6 @@ static const struct reg_t tvregs_vesa_1280x600p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -915,7 +887,6 @@ static const struct reg_t tvregs_vesa_1280x768p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x7,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -940,7 +911,6 @@ static const struct reg_t tvregs_vesa_1280x800p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -965,7 +935,6 @@ static const struct reg_t tvregs_vesa_1280x960p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -990,7 +959,6 @@ static const struct reg_t tvregs_vesa_1280x1024p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -1015,7 +983,6 @@ static const struct reg_t tvregs_vesa_1360x768p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1040,7 +1007,6 @@ static const struct reg_t tvregs_vesa_1366x768p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1065,7 +1031,6 @@ static const struct reg_t tvregs_vesa_1400x1050p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1090,7 +1055,6 @@ static const struct reg_t tvregs_vesa_1440x900p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1115,7 +1079,6 @@ static const struct reg_t tvregs_vesa_1440x2560p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1140,7 +1103,6 @@ static const struct reg_t tvregs_vesa_1440x2560p70hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1165,7 +1127,6 @@ static const struct reg_t tvregs_vesa_1600x900p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1190,7 +1151,6 @@ static const struct reg_t tvregs_vesa_1600x1200p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1215,7 +1175,6 @@ static const struct reg_t tvregs_vesa_1680x1050p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1,}, {P_ENCI_VIDEO_EN, 0,}, {MREG_END_MARKER, 0} @@ -1240,7 +1199,6 @@ static const struct reg_t tvregs_vesa_1920x1200p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -1264,7 +1222,6 @@ static const struct reg_t tvregs_vesa_2160x1200p90hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -1289,7 +1246,6 @@ static const struct reg_t tvregs_vesa_2560x1600p60hz[] = { {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -1316,7 +1272,6 @@ static const struct reg_t tvregs_vesa_2560x1080p60hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -1342,7 +1297,6 @@ static const struct reg_t tvregs_vesa_2560x1440p60hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} @@ -1368,7 +1322,6 @@ static const struct reg_t tvregs_vesa_3440x1440p60hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0} diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c index aff0b0d819..de86a7898e 100644 --- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c @@ -68,20 +68,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -355,7 +341,6 @@ void set_hdmitx_clk(enum hdmi_vic vic) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); set_hpll_od1(p_enc[j].od1); diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c index 1c972f1548..bbd9a8597f 100644 --- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include <amlogic/sound.h> #include "hdmitx_reg.h" @@ -411,7 +412,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -420,8 +421,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c index ccfd907fdb..2a57113b8e 100644 --- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/hdmitx_tvenc.c @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c index 01ed7d321c..f898dc2742 100644 --- a/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/tl1/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -424,7 +425,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -433,8 +434,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c index ec2ac574f6..4d4209c661 100644 --- a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c @@ -65,20 +65,6 @@ printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while(0); -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -345,7 +331,6 @@ void set_hdmitx_clk(enum hdmi_vic vic) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); set_hpll_od1(p_enc[j].od1); diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c index 68634d7d3f..7d4b8921b8 100644 --- a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -406,7 +407,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -415,8 +416,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c index 1de1ea117b..04a4353b1f 100644 --- a/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_tvenc.c @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c index ca12caa63c..550fd5532f 100644 --- a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c +++ b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c @@ -70,20 +70,6 @@ static uint32_t frac_rate; printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ } while (0) -// viu_channel_sel: 1 or 2 -// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - //viu_channel_sel ==2 - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - static void set_hdmitx_sys_clk(void) { hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); @@ -947,7 +933,6 @@ static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd) return; } next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); set_hdmitx_sys_clk(); set_hpll_clk_out(p_enc[j].hpll_clk_out); if (!getenv("sspll_dis")) diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c index f5da4f7b43..122f490457 100644 --- a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_set.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/register.h> +#include <amlogic/vout.h> #include <amlogic/hdmi.h> #include "hdmitx_reg.h" #include "hdmitx_tvenc.h" @@ -424,7 +425,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev) int hdmi_outputmode_check(char *mode) { - int i, ret = -1; + int i, ret = 0xff; for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { if (!strcmp(mode, gxbb_modes[i].sname)) { @@ -433,8 +434,14 @@ int hdmi_outputmode_check(char *mode) } } - if (ret) + if (ret) { printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; return ret; } diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c index 25aebf5dca..cf672dc7e5 100644 --- a/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c +++ b/arch/arm/cpu/armv8/txlx/hdmitx20/hdmitx_tvenc.c @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = { {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x407}, {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = { {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, {P_ENCP_VIDEO_EN, 0}, {P_ENCI_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_SY_VAL, 8}, {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = { {P_ENCP_VIDEO_MODE, 0x5ffc}, {P_ENCP_VIDEO_MODE_ADV, 0x0019}, {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = { {P_ENCP_VIDEO_VSO_BLINE, 0}, {P_ENCP_VIDEO_VSO_ELINE, 5}, {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_VENC_VIDEO_PROG_MODE, 0x100}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = { {P_ENCP_VIDEO_SYNC_MODE, 0x7}, {P_ENCP_VIDEO_YC_DLY, 0}, {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCI_VIDEO_EN, 0}, {P_ENCP_VIDEO_EN, 1}, {MREG_END_MARKER, 0}, @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = { {P_ENCP_VIDEO_VSO_ELINE, 53}, {P_ENCP_VIDEO_MAX_LNCNT, 2249}, {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = { {P_ENCP_VIDEO_VSO_END, 0x32,}, {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, {P_ENCP_VIDEO_EN, 1}, {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, diff --git a/arch/arm/include/asm/arch-g12a/regs.h b/arch/arm/include/asm/arch-g12a/regs.h index af9fa9b33a..25b121a4ba 100644 --- a/arch/arm/include/asm/arch-g12a/regs.h +++ b/arch/arm/include/asm/arch-g12a/regs.h @@ -24129,10 +24129,21 @@ //Bit 11:0 vertical formatter width #define VIU2_VD1_FMT_W (0x1e69) #define P_VIU2_VD1_FMT_W (volatile unsigned int *)((0x1e69 << 2) + 0xff900000) -#define VIU2_VD1_IF0_GEN_REG3 (0x1e70) -#define P_VIU2_VD1_IF0_GEN_REG3 (volatile unsigned int *)((0x1e70 << 2) + 0xff900000) -//bit 31:1, reversed -//bit 0, cntl_64bit_rev +//`define VIU2_MATRIX_CTRL 8'h70 +#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70 +#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71 +#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72 +#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73 +#define VIU2_OSD1_MATRIX_COEF22 0x1e74 +#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75 +#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76 +#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77 +#define VIU2_OSD1_MATRIX_CLIP 0x1e78 +#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79 +#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a +#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b +#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c +#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d // synopsys translate_off // synopsys translate_on // @@ -24689,6 +24700,7 @@ #define P_VPU_VIU_ASYNC_MASK (volatile unsigned int *)((0x2781 << 2) + 0xff900000) #define VDIN_MISC_CTRL (0x2782) #define P_VDIN_MISC_CTRL (volatile unsigned int *)((0x2782 << 2) + 0xff900000) +#define VPU_VENCX_CLK_CTRL 0x2785 // vpu arbtration : // the segment is 8'h90-8'hc8 // diff --git a/arch/arm/include/asm/arch-g12b/regs.h b/arch/arm/include/asm/arch-g12b/regs.h index af9fa9b33a..b75fe2f1c4 100644 --- a/arch/arm/include/asm/arch-g12b/regs.h +++ b/arch/arm/include/asm/arch-g12b/regs.h @@ -24129,10 +24129,23 @@ //Bit 11:0 vertical formatter width #define VIU2_VD1_FMT_W (0x1e69) #define P_VIU2_VD1_FMT_W (volatile unsigned int *)((0x1e69 << 2) + 0xff900000) -#define VIU2_VD1_IF0_GEN_REG3 (0x1e70) -#define P_VIU2_VD1_IF0_GEN_REG3 (volatile unsigned int *)((0x1e70 << 2) + 0xff900000) -//bit 31:1, reversed -//bit 0, cntl_64bit_rev +//`define VIU2_MATRIX_CTRL 8'h70 +#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70 +#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71 +#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72 +#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73 +#define VIU2_OSD1_MATRIX_COEF22 0x1e74 +#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75 +#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76 +#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77 +#define VIU2_OSD1_MATRIX_CLIP 0x1e78 +#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79 +#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a +#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b +#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c +#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d +#define VIU2_RMIF_CTRL0 0x1e80 +#define VIU2_RMIF_CTRL1 0x1e81 // synopsys translate_off // synopsys translate_on // @@ -24689,6 +24702,7 @@ #define P_VPU_VIU_ASYNC_MASK (volatile unsigned int *)((0x2781 << 2) + 0xff900000) #define VDIN_MISC_CTRL (0x2782) #define P_VDIN_MISC_CTRL (volatile unsigned int *)((0x2782 << 2) + 0xff900000) +#define VPU_VENCX_CLK_CTRL 0x2785 // vpu arbtration : // the segment is 8'h90-8'hc8 // diff --git a/common/cmd_vout.c b/common/cmd_vout.c index b960f1c354..caa989ae39 100644 --- a/common/cmd_vout.c +++ b/common/cmd_vout.c @@ -72,6 +72,7 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv { #ifdef CONFIG_AML_HDMITX20 char mode[64]; + int venc_sel; #endif #ifdef CONFIG_AML_LCD struct aml_lcd_drv_s *lcd_drv = NULL; @@ -82,6 +83,7 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv #ifdef CONFIG_AML_CVBS if (cvbs_outputmode_check(argv[1]) == 0) { + vout_viu_mux(VOUT_VIU1_SEL, VIU_MUX_ENCI); vpp_matrix_update(VPP_CM_YUV); if (cvbs_set_vmode(argv[1]) == 0) return CMD_RET_SUCCESS; @@ -89,7 +91,9 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv #endif #ifdef CONFIG_AML_HDMITX20 - if (hdmi_outputmode_check(argv[1]) == 0) { + venc_sel = hdmi_outputmode_check(argv[1]); + if (venc_sel < VIU_MUX_MAX) { + vout_viu_mux(VOUT_VIU1_SEL, venc_sel); vpp_matrix_update(VPP_CM_YUV); memset(mode, 0, sizeof(mode)); sprintf(mode, "hdmitx output %s", argv[1]); @@ -103,6 +107,7 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv if (lcd_drv) { if (lcd_drv->lcd_outputmode_check) { if (lcd_drv->lcd_outputmode_check(argv[1]) == 0) { + vout_viu_mux(VOUT_VIU1_SEL, VIU_MUX_ENCL); vpp_matrix_update(VPP_CM_RGB); if (lcd_drv->lcd_enable) { lcd_drv->lcd_enable(argv[1]); @@ -119,6 +124,62 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv return CMD_RET_FAILURE; } +static int do_vout2_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ +#ifdef CONFIG_AML_HDMITX20 + char mode[64]; + int venc_sel; +#endif +#ifdef CONFIG_AML_LCD + struct aml_lcd_drv_s *lcd_drv = NULL; +#endif + + if (argc != 2) + return CMD_RET_FAILURE; + +#ifdef CONFIG_AML_CVBS + if (cvbs_outputmode_check(argv[1]) == 0) { + vout_viu_mux(VOUT_VIU2_SEL, VIU_MUX_ENCI); + vpp_viu2_matrix_update(VPP_CM_YUV); + if (cvbs_set_vmode(argv[1]) == 0) + return CMD_RET_SUCCESS; + } +#endif + +#ifdef CONFIG_AML_HDMITX20 + venc_sel = hdmi_outputmode_check(argv[1]); + if (venc_sel < VIU_MUX_MAX) { + vout_viu_mux(VOUT_VIU2_SEL, venc_sel); + vpp_viu2_matrix_update(VPP_CM_YUV); + memset(mode, 0, sizeof(mode)); + sprintf(mode, "hdmitx output %s", argv[1]); + run_command(mode, 0); + return CMD_RET_SUCCESS; + } +#endif + +#ifdef CONFIG_AML_LCD + lcd_drv = aml_lcd_get_driver(); + if (lcd_drv) { + if (lcd_drv->lcd_outputmode_check) { + if (lcd_drv->lcd_outputmode_check(argv[1]) == 0) { + vout_viu_mux(VOUT_VIU2_SEL, VIU_MUX_ENCL); + vpp_viu2_matrix_update(VPP_CM_RGB); + if (lcd_drv->lcd_enable) { + lcd_drv->lcd_enable(argv[1]); + return CMD_RET_SUCCESS; + } else + printf("no lcd enable\n"); + } + } + } else { + printf("no lcd driver\n"); + } +#endif + + return CMD_RET_FAILURE; +} + static int do_vout_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { vout_vinfo_dump(); @@ -157,3 +218,35 @@ U_BOOT_CMD(vout, CONFIG_SYS_MAXARGS, 1, do_vout, " format : perfered output video mode\n" " info : dump vinfo\n" ); + +static cmd_tbl_t cmd_vout2_sub[] = { + U_BOOT_CMD_MKENT(list, 1, 1, do_vout_list, "", ""), + U_BOOT_CMD_MKENT(output, 3, 1, do_vout2_output, "", ""), + U_BOOT_CMD_MKENT(info, 1, 1, do_vout_info, "", ""), +}; + +static int do_vout2(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return cmd_usage(cmdtp); + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_vout2_sub[0], ARRAY_SIZE(cmd_vout2_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return cmd_usage(cmdtp); +} + +U_BOOT_CMD(vout2, CONFIG_SYS_MAXARGS, 1, do_vout2, + "VOUT2 sub-system", + "vout2 [list | output format | info]\n" + " list : list for valid video mode names.\n" + " format : perfered output video mode\n" + " info : dump vinfo\n" +); diff --git a/drivers/display/lcd/lcd_tablet/lcd_drv.c b/drivers/display/lcd/lcd_tablet/lcd_drv.c index 10ed53ba3b..8b784dc7f7 100644 --- a/drivers/display/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/display/lcd/lcd_tablet/lcd_drv.c @@ -162,7 +162,6 @@ static void lcd_venc_set(struct lcd_config_s *pconf) lcd_vcbus_write(ENCL_VIDEO_EN, 0); - lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2)); // viu1 select encl | viu2 select encl lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000); // bit[15] shadown en lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); // Sampling rate: 1 diff --git a/drivers/display/vout/cvbs_config.h b/drivers/display/vout/cvbs_config.h index d9b973b740..498699c733 100644 --- a/drivers/display/vout/cvbs_config.h +++ b/drivers/display/vout/cvbs_config.h @@ -340,7 +340,6 @@ static const struct reg_s tvregs_576cvbs_enc[] = { {VENC_VDAC_DACSEL3, 0x0000, }, {VENC_VDAC_DACSEL4, 0x0000, }, {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, {VENC_VDAC_FIFO_CTRL, 0x2000, }, {ENCI_DACSEL_0, 0x0011 }, {ENCI_DACSEL_1, 0x11 }, @@ -390,7 +389,6 @@ static const struct reg_s tvregs_480cvbs_enc[] = { {VENC_VDAC_DACSEL3, 0x0000, }, {VENC_VDAC_DACSEL4, 0x0000, }, {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, {VENC_VDAC_FIFO_CTRL, 0x2000, }, {ENCI_DACSEL_0, 0x0011 }, {ENCI_DACSEL_1, 0x11 }, @@ -441,7 +439,6 @@ static const struct reg_s tvregs_pal_m_enc[] = { {VENC_VDAC_DACSEL3, 0x0000,}, {VENC_VDAC_DACSEL4, 0x0000,}, {VENC_VDAC_DACSEL5, 0x0000,}, - {VPU_VIU_VENC_MUX_CTRL, 0x0005,}, {VENC_VDAC_FIFO_CTRL, 0x2000,}, {ENCI_DACSEL_0, 0x0011 }, {ENCI_DACSEL_1, 0x11 }, @@ -492,7 +489,6 @@ static const struct reg_s tvregs_pal_n_enc[] = { {VENC_VDAC_DACSEL3, 0x0000, }, {VENC_VDAC_DACSEL4, 0x0000, }, {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, {VENC_VDAC_FIFO_CTRL, 0x2000, }, {ENCI_DACSEL_0, 0x0011 }, {ENCI_DACSEL_1, 0x11 }, diff --git a/drivers/display/vout/vout.c b/drivers/display/vout/vout.c index c3c395440e..2d06a531d9 100644 --- a/drivers/display/vout/vout.c +++ b/drivers/display/vout/vout.c @@ -17,8 +17,9 @@ * */ - +#include <asm/cpu_id.h> #include <common.h> +#include <vpp.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> #include <amlogic/vmode.h> @@ -38,6 +39,7 @@ #define REG_OFFSET_VCBUS(reg) ((reg << 2)) #define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) +#define REG_ADDR_HIU(reg) (reg + 0L) static int g_vmode = -1; @@ -47,6 +49,8 @@ typedef struct vout_set_s { ulong width; ulong height; ulong field_height; + int viu_color_fmt; + enum viu_mux_e viu_mux; } vout_set_t; @@ -57,6 +61,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 480, .field_height = 240, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_480CVBS*/ .name = "480cvbs", @@ -64,6 +70,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 480, .field_height = 240, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_480P */ .name = "480p", @@ -71,6 +79,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 480, .field_height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_576I */ .name = "576i", @@ -78,6 +88,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 576, .field_height = 288, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_576I */ .name = "576cvbs", @@ -85,6 +97,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 576, .field_height = 288, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_576P */ .name = "576p", @@ -92,6 +106,8 @@ static const vout_set_t vout_sets[] = { .width = 720, .height = 576, .field_height = 576, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_720P */ .name = "720p", @@ -99,6 +115,8 @@ static const vout_set_t vout_sets[] = { .width = 1280, .height = 720, .field_height = 720, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_768P */ .name = "768p", @@ -106,6 +124,8 @@ static const vout_set_t vout_sets[] = { .width = 1366, .height = 768, .field_height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1080I */ .name = "1080i", @@ -113,6 +133,8 @@ static const vout_set_t vout_sets[] = { .width = 1920, .height = 1080, .field_height = 540, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1080P */ .name = "1080p", @@ -120,6 +142,8 @@ static const vout_set_t vout_sets[] = { .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_4K2K_60HZ */ .name = "2160p", @@ -127,6 +151,8 @@ static const vout_set_t vout_sets[] = { .width = 3840, .height = 2160, .field_height = 2160, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_4K2K_SMPTE */ .name = "smpte", @@ -134,6 +160,8 @@ static const vout_set_t vout_sets[] = { .width = 4096, .height = 2160, .field_height = 2160, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_vga */ .name = "vga", @@ -141,6 +169,8 @@ static const vout_set_t vout_sets[] = { .width = 640, .height = 480, .field_height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_SVGA */ .name = "svga", @@ -148,6 +178,8 @@ static const vout_set_t vout_sets[] = { .width = 800, .height = 600, .field_height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_XGA */ .name = "xga", @@ -155,6 +187,8 @@ static const vout_set_t vout_sets[] = { .width = 1024, .height = 768, .field_height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_sxga */ .name = "sxga", @@ -162,6 +196,8 @@ static const vout_set_t vout_sets[] = { .width = 1280, .height = 1024, .field_height = 1024, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_wsxga */ .name = "wsxga", @@ -169,6 +205,8 @@ static const vout_set_t vout_sets[] = { .width = 1440, .height = 900, .field_height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_fhdvga */ .name = "fhdvga", @@ -176,6 +214,8 @@ static const vout_set_t vout_sets[] = { .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_LCD */ .name = "panel", @@ -183,144 +223,192 @@ static const vout_set_t vout_sets[] = { .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_640x480p60hz */ .name = "640x480p60hz", .mode = VMODE_640x480p60hz, .width = 640, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_800x480p60hz */ .name = "800x480p60hz", .mode = VMODE_800x480p60hz, .width = 800, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_800x600p60hz */ .name = "800x600p60hz", .mode = VMODE_800x600p60hz, .width = 800, .height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_852x480p60hz */ .name = "852x480p60hz", .mode = VMODE_852x480p60hz, .width = 852, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_854x480p60hz */ .name = "854x480p60hz", .mode = VMODE_854x480p60hz, .width = 854, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1024x768p60hz */ .name = "1024x768p60hz", .mode = VMODE_1024x768p60hz, .width = 1024, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1152x864p75hz */ .name = "1152x864p75hz", .mode = VMODE_1152x864p75hz, .width = 1152, .height = 864, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x600p60hz */ .name = "1280x600p60hz", .mode = VMODE_1280x600p60hz, .width = 1280, .height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x768p60hz */ .name = "1280x768p60hz", .mode = VMODE_1280x768p60hz, .width = 1280, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x800p60hz */ .name = "1280x800p60hz", .mode = VMODE_1280x800p60hz, .width = 1280, .height = 800, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x960p60hz */ .name = "1280x960p60hz", .mode = VMODE_1280x960p60hz, .width = 1280, .height = 960, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x1024p60hz */ .name = "1280x1024p60hz", .mode = VMODE_1280x1024p60hz, .width = 1280, .height = 1024, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1360x768p60hz */ .name = "1360x768p60hz", .mode = VMODE_1360x768p60hz, .width = 1360, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1366x768p60hz */ .name = "1366x768p60hz", .mode = VMODE_1366x768p60hz, .width = 1366, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1400x1050p60hz */ .name = "1400x1050p60hz", .mode = VMODE_1400x1050p60hz, .width = 1400, .height = 1050, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x900p60hz */ .name = "1440x900p60hz", .mode = VMODE_1440x900p60hz, .width = 1440, .height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x2560p60hz */ .name = "1440x2560p60hz", .mode = VMODE_1440x2560p60hz, .width = 1440, .height = 2560, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x2560p70hz */ .name = "1440x2560p70hz", .mode = VMODE_1440x2560p70hz, .width = 1440, .height = 2560, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1600x900p60hz */ .name = "1600x900p60hz", .mode = VMODE_1600x900p60hz, .width = 1600, .height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1600x1200p60hz */ .name = "1600x1200p60hz", .mode = VMODE_1600x1200p60hz, .width = 1600, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1680x1050p60hz */ .name = "1680x1050p60hz", .mode = VMODE_1680x1050p60hz, .width = 1680, .height = 1050, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1920x1200p60hz */ .name = "1920x1200p60hz", .mode = VMODE_1920x1200p60hz, .width = 1920, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_2160x1200p90hz */ .name = "2160x1200p90hz", .mode = VMODE_2160x1200p90hz, .width = 2160, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_2560x1600p60hz */ .name = "2560x1600p60hz", @@ -339,6 +427,8 @@ static const vout_set_t vout_sets[] = { .mode = VMODE_2560x1080p60hz, .width = 2560, .height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1024x600p60hz */ .name = "1024x600p60hz", @@ -371,11 +461,49 @@ static struct vinfo_s vout_info = { .priv = NULL, /* Pointer to driver-specific data */ }; +#ifndef HHI_VPU_CLKC_CNTL +#define HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2)) +#endif +#ifndef VPU_VENCX_CLK_CTRL +#define VPU_VENCX_CLK_CTRL 0x2785 +#endif + +static inline unsigned int vout_reg_read(u32 reg) +{ + return (*(volatile unsigned int *)REG_ADDR_VCBUS(reg)); +} + static inline void vout_reg_write(u32 reg, const u32 val) { *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val); } +static inline void vout_reg_setb(unsigned int reg, unsigned int val, + unsigned int start, unsigned int len) +{ + vout_reg_write(reg, ((vout_reg_read(reg) & + ~(((1L << (len))-1) << (start))) | + (((val)&((1L<<(len))-1)) << (start)))); +} + +static inline unsigned int vout_hiu_read(u32 reg) +{ + return *(volatile unsigned int *)(REG_ADDR_HIU(reg)); +} + +static inline void vout_hiu_write(u32 reg, const u32 val) +{ + *(volatile unsigned int *)REG_ADDR_HIU(reg) = (val); +} + +static inline void vout_hiu_setb(unsigned int reg, unsigned int val, + unsigned int start, unsigned int len) +{ + vout_hiu_write(reg, ((vout_hiu_read(reg) & + ~(((1L << (len))-1) << (start))) | + (((val)&((1L<<(len))-1)) << (start)))); +} + static int vout_find_mode_by_name(const char *name) { int mode = -1; @@ -637,6 +765,66 @@ void vout_vinfo_dump(void) vout_log("vinfo.vd_color_bg: %d\n", info->vd_color_bg); } +void vout_viu_mux(int viu_sel, int venc_sel) +{ + unsigned int mux_bit = 0xff; + unsigned int clk_bit = 0xff, clk_sel = 0; + unsigned int viu2_valid = 0; + + switch (get_cpu_id().family_id) { + case MESON_CPU_MAJOR_ID_G12A: + case MESON_CPU_MAJOR_ID_G12B: + viu2_valid = 1; + break; + default: + break; + } + + switch (viu_sel) { + case VOUT_VIU2_SEL: + if (viu2_valid) { + /* set cts_vpu_clkc to 200MHz*/ + vout_hiu_setb(HHI_VPU_CLKC_CNTL, 2, 9, 3); + vout_hiu_setb(HHI_VPU_CLKC_CNTL, 1, 0, 1); + vout_hiu_setb(HHI_VPU_CLKC_CNTL, 1, 8, 3); + mux_bit = 2; + clk_sel = 1; + } + break; + case VOUT_VIU1_SEL: + if (viu2_valid) + vout_hiu_setb(HHI_VPU_CLKC_CNTL, 0, 8, 1); + mux_bit = 0; + clk_sel = 0; + break; + default: + break; + } + + switch (venc_sel) { + case VIU_MUX_ENCL: + clk_bit = 1; + break; + case VIU_MUX_ENCI: + clk_bit = 2; + break; + case VIU_MUX_ENCP: + clk_bit = 0; + break; + default: + break; + } + + vout_reg_setb(VPU_VIU_VENC_MUX_CTRL, 0xf, 0, 4); + if (mux_bit < 0xff) + vout_reg_setb(VPU_VIU_VENC_MUX_CTRL, venc_sel, mux_bit, 2); + + if (viu2_valid) { + if (clk_bit < 0xff) + vout_reg_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1); + } +} + void vout_init(void) { vout_logl(); diff --git a/drivers/vpp/aml_vpp.c b/drivers/vpp/aml_vpp.c index 8600ef23a2..01ca4f191f 100644 --- a/drivers/vpp/aml_vpp.c +++ b/drivers/vpp/aml_vpp.c @@ -1046,7 +1046,7 @@ for G12A, set osd2 matrix(10bit) RGB2YUV RGB709_to_YUV709l_coeff, CSC_ON); } - } +} /* for G12A, set osd2 matrix(10bit) RGB2YUV @@ -1124,6 +1124,37 @@ static void set_osd3_rgb2yuv(bool on) } } +static void set_viu2_osd_matrix_rgb2yuv(bool on) +{ + int *m = RGB709_to_YUV709l_coeff; + + /* RGB -> 709 limit */ + if (is_osd_high_version()) { + /* VPP WRAP OSD3 matrix */ + vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff)); + vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF22, + m[11] & 0x1fff); + + vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff)); + vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET2, + m[20] & 0xfff); + + vpp_reg_setb(VIU2_OSD1_MATRIX_EN_CTRL, on, 0, 1); + } +} + /* for txlx, set vpp default data path to u10 */ @@ -1435,6 +1466,30 @@ void vpp_matrix_update(int type) } } +void vpp_viu2_matrix_update(int type) +{ + if (vpp_init_flag == 0) + return; + + if (get_cpu_id().family_id < MESON_CPU_MAJOR_ID_G12A) + return; + + VPP_PR("%s: %d\n", __func__, type); + + switch (type) { + case VPP_CM_RGB: + /* default RGB */ + set_viu2_osd_matrix_rgb2yuv(0); + break; + case VPP_CM_YUV: + /* RGB to 709 limit */ + set_viu2_osd_matrix_rgb2yuv(1); + break; + default: + break; + } +} + static void vpp_ofifo_init(void) { unsigned int data32; diff --git a/drivers/vpp/aml_vpp_reg.h b/drivers/vpp/aml_vpp_reg.h index 05b625c453..b726ef976d 100644 --- a/drivers/vpp/aml_vpp_reg.h +++ b/drivers/vpp/aml_vpp_reg.h @@ -209,6 +209,10 @@ #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd #endif +#ifndef VPU_VENCX_CLK_CTRL +#define VPU_VENCX_CLK_CTRL 0x2785 +#endif + #ifndef DOLBY_PATH_CTRL #define DOLBY_PATH_CTRL 0x1a0c #endif @@ -336,6 +340,49 @@ #define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db #define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc +#ifndef VIU2_OSD1_MATRIX_COEF00_01 +#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF02_10 +#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF11_12 +#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF20_21 +#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF22 +#define VIU2_OSD1_MATRIX_COEF22 0x1e74 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF13_14 +#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF23_24 +#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF15_25 +#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77 +#endif +#ifndef VIU2_OSD1_MATRIX_CLIP +#define VIU2_OSD1_MATRIX_CLIP 0x1e78 +#endif +#ifndef VIU2_OSD1_MATRIX_OFFSET0_1 +#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79 +#endif +#ifndef VIU2_OSD1_MATRIX_OFFSET2 +#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a +#endif +#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET0_1 +#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b +#endif +#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET2 +#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c +#endif +#ifndef VIU2_OSD1_MATRIX_EN_CTRL +#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d +#endif + /*hdr2 register end*/ //#define GAMMA_CNTL_PORT 0x1400 diff --git a/include/amlogic/vout.h b/include/amlogic/vout.h index 9c410e0ea7..80d36b3c8e 100644 --- a/include/amlogic/vout.h +++ b/include/amlogic/vout.h @@ -3,12 +3,23 @@ #include <amlogic/vinfo.h> +#define VOUT_VIU1_SEL 1 +#define VOUT_VIU2_SEL 2 + +enum viu_mux_e { + VIU_MUX_ENCL = 0, + VIU_MUX_ENCI, + VIU_MUX_ENCP, + VIU_MUX_MAX, +}; + void vout_init(void); void vout_vinfo_dump(void); int vout_get_current_vmode(void); int vout_get_current_axis(int *axis); void vout_set_current_vmode(int mode); struct vinfo_s *vout_get_current_vinfo(void); +extern void vout_viu_mux(int viu_sel, int venc_sel); extern unsigned long get_fb_addr(void); #endif diff --git a/include/vpp.h b/include/vpp.h index 33f5596ed0..40df77d71f 100644 --- a/include/vpp.h +++ b/include/vpp.h @@ -9,6 +9,7 @@ void vpp_pq_load(void); #define VPP_CM_YUV 2 /* same as COLOR_FMT_YUV444*/ extern void vpp_matrix_update(int type); +extern void vpp_viu2_matrix_update(int type); enum vpp_gamma_sel_e { VPP_GAMMA_R = 0, |