summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorHang Cheng <hang.cheng@amlogic.com>2019-06-29 20:50:20 +0800
committerDongjin Kim <tobetter@gmail.com>2020-02-18 13:03:34 +0900
commit219729b117019299817b55062e7af451aa88e289 (patch)
treeb7bd5174cae2627e76904cb5ce5b7a2f0abde826
parent113439af73ff74ea0b96bc24e2ecc68199f7fec4 (diff)
downloadu-boot-odroid-c1-219729b117019299817b55062e7af451aa88e289.tar.gz
hdmitx: correct vid pll div shift preset length [3/3]
PD#SWPL-9589 Problem: shift preset length of vid pll div is wrong Solution: modify shift preset length of vid pll div Verify: gxl-p281 Change-Id: Ibac6efe889630d32c30219618daa1f4d994a67bf Signed-off-by: Hang Cheng <hang.cheng@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
Diffstat
-rw-r--r--arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c4
-rw-r--r--arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c4
8 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
index 4d4209c661..c1d810443f 100644
--- a/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
@@ -230,11 +230,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
index c5bf713ce1..c333419c95 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
@@ -628,11 +628,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
index 47da9e9e13..b138541f6e 100644
--- a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
@@ -627,11 +627,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
index 7590a5f9e0..b44cbfc428 100644
--- a/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxb/hdmitx20/enc_clk_config.c
@@ -258,11 +258,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
index da6964d482..ee5feb6c34 100644
--- a/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxl/hdmitx20/enc_clk_config.c
@@ -597,11 +597,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
index de86a7898e..04ae2cb907 100644
--- a/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/gxtvbb/hdmitx20/enc_clk_config.c
@@ -240,11 +240,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
index 4d4209c661..c1d810443f 100644
--- a/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/txl/hdmitx20/enc_clk_config.c
@@ -230,11 +230,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
diff --git a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
index 550fd5532f..378144b17e 100644
--- a/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/txlx/hdmitx20/enc_clk_config.c
@@ -597,11 +597,11 @@ static void set_hpll_od3_clk_div(int div_sel)
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
+ hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
// Enable the final output clock
View Lorry Controller Status