diff options
Diffstat (limited to 'chromium/third_party/libdrm/src/intel/intel_chipset.h')
| -rw-r--r-- | chromium/third_party/libdrm/src/intel/intel_chipset.h | 83 |
1 files changed, 10 insertions, 73 deletions
diff --git a/chromium/third_party/libdrm/src/intel/intel_chipset.h b/chromium/third_party/libdrm/src/intel/intel_chipset.h index 514f6594a15..26fbee4db50 100644 --- a/chromium/third_party/libdrm/src/intel/intel_chipset.h +++ b/chromium/third_party/libdrm/src/intel/intel_chipset.h @@ -168,7 +168,6 @@ #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ -#define PCI_CHIP_SKYLAKE_H_GT1 0x190B #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ @@ -180,43 +179,17 @@ #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 -#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 -#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 -#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A +#define PCI_CHIP_SKYLAKE_GT3 0x1926 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D +#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A #define PCI_CHIP_SKYLAKE_H_GT4 0x193B #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D -#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 -#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 -#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 -#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E -#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 -#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 -#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B -#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D - #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 -#define PCI_CHIP_BROXTON_3 0x1A85 -#define PCI_CHIP_BROXTON_4 0x5A85 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -377,11 +350,10 @@ #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ IS_CHERRYVIEW(devid)) -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) +#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ @@ -394,11 +366,8 @@ (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) +#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_GT3 || \ + (devid) == PCI_CHIP_SKYLAKE_HALO_GT3) #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ @@ -406,35 +375,6 @@ (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) - -#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) - -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) - -#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ - IS_KBL_GT2(devid) || \ - IS_KBL_GT3(devid) || \ - IS_KBL_GT4(devid)) - #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ IS_SKL_GT3(devid) || \ @@ -442,13 +382,10 @@ #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ (devid) == PCI_CHIP_BROXTON_1 || \ - (devid) == PCI_CHIP_BROXTON_2 || \ - (devid) == PCI_CHIP_BROXTON_3 || \ - (devid) == PCI_CHIP_BROXTON_4) + (devid) == PCI_CHIP_BROXTON_2) #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ - IS_BROXTON(devid) || \ - IS_KABYLAKE(devid)) + IS_BROXTON(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ |