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| author | Allan Sandfeld Jensen <allan.jensen@qt.io> | 2017-12-08 10:22:59 +0100 |
|---|---|---|
| committer | Allan Sandfeld Jensen <allan.jensen@qt.io> | 2017-12-08 12:17:14 +0000 |
| commit | 69b8f9169ffd66fdeca1ac60a4bc06b91d106186 (patch) | |
| tree | c8b7f735583d0b4e0c0b61a014a7f4b3b26e85ab /chromium/v8/src/arm/assembler-arm.cc | |
| parent | daa093eea7c773db06799a13bd7e4e2e2a9f8f14 (diff) | |
| download | qtwebengine-chromium-69b8f9169ffd66fdeca1ac60a4bc06b91d106186.tar.gz | |
BASELINE: Update Chromium to 63.0.3239.87
Change-Id: Iac27464730121b4fac76869d87d622504642e016
Reviewed-by: Peter Varga <pvarga@inf.u-szeged.hu>
Diffstat (limited to 'chromium/v8/src/arm/assembler-arm.cc')
| -rw-r--r-- | chromium/v8/src/arm/assembler-arm.cc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/chromium/v8/src/arm/assembler-arm.cc b/chromium/v8/src/arm/assembler-arm.cc index 9799950728d..c9aa9ef015c 100644 --- a/chromium/v8/src/arm/assembler-arm.cc +++ b/chromium/v8/src/arm/assembler-arm.cc @@ -2131,6 +2131,8 @@ void Assembler::strd(Register src1, Register src2, void Assembler::ldrex(Register dst, Register src, Condition cond) { // Instruction details available in ARM DDI 0406C.b, A8.8.75. // cond(31-28) | 00011001(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0) + DCHECK(dst != pc); + DCHECK(src != pc); emit(cond | B24 | B23 | B20 | src.code() * B16 | dst.code() * B12 | 0xf9f); } @@ -2139,6 +2141,11 @@ void Assembler::strex(Register src1, Register src2, Register dst, // Instruction details available in ARM DDI 0406C.b, A8.8.212. // cond(31-28) | 00011000(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) | // Rt(3-0) + DCHECK(dst != pc); + DCHECK(src1 != pc); + DCHECK(src2 != pc); + DCHECK(src1 != dst); + DCHECK(src1 != src2); emit(cond | B24 | B23 | dst.code() * B16 | src1.code() * B12 | 0xf9 * B4 | src2.code()); } @@ -2146,6 +2153,8 @@ void Assembler::strex(Register src1, Register src2, Register dst, void Assembler::ldrexb(Register dst, Register src, Condition cond) { // Instruction details available in ARM DDI 0406C.b, A8.8.76. // cond(31-28) | 00011101(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0) + DCHECK(dst != pc); + DCHECK(src != pc); emit(cond | B24 | B23 | B22 | B20 | src.code() * B16 | dst.code() * B12 | 0xf9f); } @@ -2155,6 +2164,11 @@ void Assembler::strexb(Register src1, Register src2, Register dst, // Instruction details available in ARM DDI 0406C.b, A8.8.213. // cond(31-28) | 00011100(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) | // Rt(3-0) + DCHECK(dst != pc); + DCHECK(src1 != pc); + DCHECK(src2 != pc); + DCHECK(src1 != dst); + DCHECK(src1 != src2); emit(cond | B24 | B23 | B22 | dst.code() * B16 | src1.code() * B12 | 0xf9 * B4 | src2.code()); } @@ -2162,6 +2176,8 @@ void Assembler::strexb(Register src1, Register src2, Register dst, void Assembler::ldrexh(Register dst, Register src, Condition cond) { // Instruction details available in ARM DDI 0406C.b, A8.8.78. // cond(31-28) | 00011111(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0) + DCHECK(dst != pc); + DCHECK(src != pc); emit(cond | B24 | B23 | B22 | B21 | B20 | src.code() * B16 | dst.code() * B12 | 0xf9f); } @@ -2171,6 +2187,11 @@ void Assembler::strexh(Register src1, Register src2, Register dst, // Instruction details available in ARM DDI 0406C.b, A8.8.215. // cond(31-28) | 00011110(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) | // Rt(3-0) + DCHECK(dst != pc); + DCHECK(src1 != pc); + DCHECK(src2 != pc); + DCHECK(src1 != dst); + DCHECK(src1 != src2); emit(cond | B24 | B23 | B22 | B21 | dst.code() * B16 | src1.code() * B12 | 0xf9 * B4 | src2.code()); } |