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| author | Denis Shienkov <denis.shienkov@gmail.com> | 2020-10-01 18:34:53 +0300 |
|---|---|---|
| committer | Denis Shienkov <denis.shienkov@gmail.com> | 2020-10-01 16:00:03 +0000 |
| commit | cdc38bc70d42c0f10be5846323d86477e93abe13 (patch) | |
| tree | 58b0bdc06eabbfd04b75d5a6972147c6f53159e0 | |
| parent | 5132d80c848a2d9a04b4f058b80382bc7c2245d4 (diff) | |
| download | qbs-cdc38bc70d42c0f10be5846323d86477e93abe13.tar.gz | |
baremetal: Fix startup code for PCA10040 board using Keil toolchain
Change-Id: I09d3d3edbcdb3d1e5ae82fce4d204a174dfda5bb
Reviewed-by: Ivan Komissarov <ABBAPOH@gmail.com>
| -rw-r--r-- | examples/baremetal/pca10040/greenblink/keil/startup.s | 349 |
1 files changed, 111 insertions, 238 deletions
diff --git a/examples/baremetal/pca10040/greenblink/keil/startup.s b/examples/baremetal/pca10040/greenblink/keil/startup.s index c4a197d43..369ca96f8 100644 --- a/examples/baremetal/pca10040/greenblink/keil/startup.s +++ b/examples/baremetal/pca10040/greenblink/keil/startup.s @@ -80,7 +80,7 @@ _vectors_table DCD 0 ; Reserved. DCD 0 ; Reserved. DCD 0 ; SVC. - DCD 0 ; Reserved. + DCD 0 ; Debug monitor. DCD 0 ; Reserved. DCD 0 ; PendSV. DCD 0 ; SysTick. @@ -88,243 +88,116 @@ _vectors_table DCD 0 ; Power clock. DCD 0 ; Radio. DCD 0 ; UARTE0/UART0. - DCD 0 ; SPIM0/SPIS0/TWIM0/TWIS0/SPI0/TWI0 - DCD 0 ; SPIM1/SPIS1/TWIM1/TWIS1/SPI1/TWI1 - DCD 0 ; NFCT - DCD 0 ; GPIOTE - DCD 0 ; SAADC - DCD 0 ; TIMER0 - DCD 0 ; TIMER1 - DCD 0 ; TIMER2 - DCD 0 ; RTC0 - DCD 0 ; TEMP - DCD 0 ; RNG - DCD 0 ; ECB - DCD 0 ; CCM/AAR - DCD 0 ; WDT - DCD 0 ; RTC1 - DCD 0 ; QDEC - DCD 0 ; COMP/LPCOMP - DCD 0 ; SWI0/EGU0 - DCD 0 ; SWI1/EGU1 - DCD 0 ; SWI2/EGU2 - DCD 0 ; SWI3/EGU3 - DCD 0 ; SWI4/EGU4 - DCD 0 ; SWI5/EGU5 - DCD 0 ; TIMER3 - DCD 0 ; TIMER4 - DCD 0 ; PWM0 - DCD 0 ; PDM - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; MWU - DCD 0 ; PWM1 - DCD 0 ; PWM2 - DCD 0 ; SPIM2/SPIS2/SPI2 - DCD 0 ; RTC2 - DCD 0 ; I2S - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD 0 ; SPIM0/SPIS0/TWIM0/TWIS0/SPI0/TWI0. + DCD 0 ; SPIM1/SPIS1/TWIM1/TWIS1/SPI1/TWI1. + DCD 0 ; NFCT. + DCD 0 ; GPIOTE. + DCD 0 ; SAADC. + DCD 0 ; TIMER0. + DCD 0 ; TIMER1. + DCD 0 ; TIMER2. + DCD 0 ; RTC0. + DCD 0 ; TEMP. + DCD 0 ; RNG. + DCD 0 ; ECB. + DCD 0 ; CCM/AAR. + DCD 0 ; WDT. + DCD 0 ; RTC1. + DCD 0 ; QDEC. + DCD 0 ; COMP/LPCOMP. + DCD 0 ; SWI0/EGU0. + DCD 0 ; SWI1/EGU1. + DCD 0 ; SWI2/EGU2. + DCD 0 ; SWI3/EGU3. + DCD 0 ; SWI4/EGU4. + DCD 0 ; SWI5/EGU5. + DCD 0 ; TIMER3. + DCD 0 ; TIMER4. + DCD 0 ; PWM0. + DCD 0 ; PDM. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; MWU. + DCD 0 ; PWM1. + DCD 0 ; PWM2. + DCD 0 ; SPIM2/SPIS2/SPI2. + DCD 0 ; RTC2. + DCD 0 ; I2S. + DCD 0 ; FPU. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + DCD 0 ; Reserved. + _end_of_vectors_table _size_of_vectors_table EQU _end_of_vectors_table - _vectors_table |