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The class looks like:
class class_identifier [#(param_decls)] [extends class_identifier #(params)];
...
endclass [: class_identifier]
Using the same Java convention of Keyword.Declaration and Name.Class.
Add a test_systemverilog_classes unit test to test_hdl.
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* Move SystemVerilog type keywords
Put them next to the generic keywords list.
* Change a couple SystemVerilog keywords to operators
The 'inside' and 'dist' keywords are described as operators in the
SystemVerilog standard, below unary increment/decrement, and above
concatenation in precedence.
See 1800-2017 tables 11-1 and 11-2 for a list of operators.
This matches the description of pygemnts Operator.Word token:
"For any operator that is a word (e.g. not)."
* Add a SystemVerilog operators unit test
Copy/paste the contents of 1800-2017 Table 11-2,
and see what the SV lexer chops it up into.
I made lots of comments for potential improvements.
Some operators, such as '[' and '.' are being labeled as punctuation.
Also, multi-character operators such as '<<<=' are being split up
into multiple, single-character tokens, eg '<' '<' '<' '='.
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Most of the contents of these two unit tests are static.
Move things around so the entire test fits on a single page,
for better readability/maintainability.
Name the code part <TEST_NAME>_TEXT,
and the tokens part <TEST_NAME>_TOKENS.
Choosing "text" b/c it's the parameter name to the
lexer.get_tokens(text) method.
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The original implementation was missing some of the more arcane features
such as underbars, the character 's' for signed/unsigned, support for
spaces before/after the base specifier, capital letter base specifiers
(ie 'B 'D 'H), and the 4-state 'xXzZ?' characters.
For regular integers, the 'l' and 'L' suffixes are not valid.
That is, unlike C, in Verilog '42L' is not a valid int literal.
Create a new test that exercises most of the interesting kinds of
SystemVerilog numbers.
This fixes a couple minor issues with what type of number the lexer
returns. For example, Numbers like '42' used to return Integer.Hex,
but now return Integer.Decimal.
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* Fix a few SystemVerilog type keywords
First, add a few missing type keywords:
chandle, const, event, string, time, type, var, void
These are most of the 'variable' types listed in 1800-2017 6.8
"Variable declarations".
Currently, this 'Keyword.Type' is not taking effect because the lexer is
finding these keywords in the 'Keyword' list above.
Remove the double declaration so we get the more specific token type.
* Change signed/unsigned to Keyword.Type
This is what the C/C++ lexer does, so it seems legit.
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* Add a basic SystemVerilog unit test
* Fix docstring
Calling it a "complete fragment" didn't make much sense.
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