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| author | Sayed Adel <seiko@imavr.com> | 2020-12-29 02:01:12 +0000 |
|---|---|---|
| committer | Sayed Adel <seiko@imavr.com> | 2020-12-29 03:58:48 +0000 |
| commit | 14385cdb4186c0636ad44532afa953473597dab8 (patch) | |
| tree | 8b051009ae6a1e115681a57469e96dd5c22af591 | |
| parent | a31071b0b4c8a6f5cb5999b6e04f5ba6057fd546 (diff) | |
| download | numpy-14385cdb4186c0636ad44532afa953473597dab8.tar.gz | |
BUG, SIMD: Fix _simd module build for 64bit ARM/NEON clang
| -rw-r--r-- | numpy/core/src/_simd/_simd_easyintrin.inc | 4 | ||||
| -rw-r--r-- | numpy/core/src/common/simd/neon/operators.h | 12 | ||||
| -rw-r--r-- | numpy/core/tests/test_simd.py | 13 |
3 files changed, 18 insertions, 11 deletions
diff --git a/numpy/core/src/_simd/_simd_easyintrin.inc b/numpy/core/src/_simd/_simd_easyintrin.inc index f83d7a286..4521b2d87 100644 --- a/numpy/core/src/_simd/_simd_easyintrin.inc +++ b/numpy/core/src/_simd/_simd_easyintrin.inc @@ -87,10 +87,10 @@ simd_arg_converter, &arg1, \ simd_arg_converter, &arg2 \ )) return NULL; \ - simd_data data; \ + simd_data data = {.u64 = 0}; \ data.RET = NPY_CAT(SIMD__IMPL_COUNT_, CONST_RNG)( \ SIMD__REPEAT_2IMM, NAME, IN0 \ - ) npyv_##NAME(arg1.data.IN0, 0); \ + ) data.RET; \ simd_arg_free(&arg1); \ simd_arg ret = { \ .data = data, .dtype = simd_data_##RET \ diff --git a/numpy/core/src/common/simd/neon/operators.h b/numpy/core/src/common/simd/neon/operators.h index 280c5e0da..b43ba3653 100644 --- a/numpy/core/src/common/simd/neon/operators.h +++ b/numpy/core/src/common/simd/neon/operators.h @@ -34,12 +34,12 @@ #define npyv_shr_s64(A, C) vshlq_s64(A, npyv_setall_s64(-(C))) // right by an immediate constant -#define npyv_shri_u16(VEC, C) ((C) == 0 ? VEC : vshrq_n_u16(VEC, C)) -#define npyv_shri_s16(VEC, C) ((C) == 0 ? VEC : vshrq_n_s16(VEC, C)) -#define npyv_shri_u32(VEC, C) ((C) == 0 ? VEC : vshrq_n_u32(VEC, C)) -#define npyv_shri_s32(VEC, C) ((C) == 0 ? VEC : vshrq_n_s32(VEC, C)) -#define npyv_shri_u64(VEC, C) ((C) == 0 ? VEC : vshrq_n_u64(VEC, C)) -#define npyv_shri_s64(VEC, C) ((C) == 0 ? VEC : vshrq_n_s64(VEC, C)) +#define npyv_shri_u16 vshrq_n_u16 +#define npyv_shri_s16 vshrq_n_s16 +#define npyv_shri_u32 vshrq_n_u32 +#define npyv_shri_s32 vshrq_n_s32 +#define npyv_shri_u64 vshrq_n_u64 +#define npyv_shri_s64 vshrq_n_s64 /*************************** * Logical diff --git a/numpy/core/tests/test_simd.py b/numpy/core/tests/test_simd.py index 71356f812..23a5bb6c3 100644 --- a/numpy/core/tests/test_simd.py +++ b/numpy/core/tests/test_simd.py @@ -173,14 +173,21 @@ class _SIMD_INT(_Test_Utility): # left shift shl = self.shl(vdata_a, count) assert shl == data_shl_a - # left shift by an immediate constant - shli = self.shli(vdata_a, count) - assert shli == data_shl_a # load to cast data_shr_a = self.load([a >> count for a in data_a]) # right shift shr = self.shr(vdata_a, count) assert shr == data_shr_a + + # shift by zero or max or out-range immediate constant is not applicable and illogical + for count in range(1, self._scalar_size()): + # load to cast + data_shl_a = self.load([a << count for a in data_a]) + # left shift by an immediate constant + shli = self.shli(vdata_a, count) + assert shli == data_shl_a + # load to cast + data_shr_a = self.load([a >> count for a in data_a]) # right shift by an immediate constant shri = self.shri(vdata_a, count) assert shri == data_shr_a |