| Commit message (Collapse) | Author | Age | Files | Lines |
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This is tricky, because we have to translate between old and new
format of struct pci_filter. At least, I added several RFU fields
so this hopefully won't have to happen again soon.
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Extend the 'filter by device ID' functionality to allow optional
specification of a device ID. For example, to list all USB controllers
in the system made by Intel, specify:
lspci -d 8086::0c03
Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
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We do not call .IX as it's not defined in mandoc.
Ellipsis at the end of line is protected by \&.
Inspired by Debian patches for the following bugs:
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=674708
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=675087
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HWDB is now handled in a way very similar to the DNS resolver.
The interface lives in a separate source file (lib/names-hwdb.c),
results of lookups are cached. Use of HWDB can be disabled either
by passing PCI_LOOKUP_NO_HWDB or by setting the hwdb.disabled
configuration parameter.
Also, there should be no more leaks of libudev's structures.
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This lets you select hwdb support at compile time.
hwdb is an efficient hardware database shipped with recent versions of udev. It contains
among other sources pci.ids so querying hwdb rather than reading pci.ids directly should give
the same result.
Ideally Linux distros using udev could stop shipping pci.ids, but use hwdb as the only source
of this information, which this patch allows.
Cc: Martin Mares <mj@ucw.cz>
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The previous implementation handled labels differently from all
other device properties, which was illogical.
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I hope that I got the attribution right.
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The original patch by Apple did not support building shared libraries on
Darwin. This corrects that oversight. It also fixes a few other
miscellaneous issues like incorrect platform detection and the lack of
an entry in the README file.
Signed-off-by: Richard Yao <ryao@gentoo.org>
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Apple published a patch that adds Darwin support to pciutils. It is not
complete, but it does not appear to cause a build failure on other
platforms. For the sake of attribution purposes, it is being kept
separate from additional changes to make pciutils build properly on
Darwin.
https://www.opensource.apple.com/source/IOPCIFamily/IOPCIFamily-224.92.1/tools/pciutils3.2.0.patch.c
This patch differs slightly from Apple's original patch by omitting the
Makefile.rej that Apple had incorrectly included in the patch that it
placed on its server.
Signed-off-by: Richard Yao <ryao@gentoo.org>
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Patch by Philip Brown.
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lspci incorrectly tests bit 4, not bit 0, for "CRS Software Visibility" in
the Root Capabilities register, so it shows "RootCap: CRSVisible-" even for
devices that do support Software Visibility.
Use the correct definition for PCI_EXP_RTCAP_CRSVIS.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Bridges can implement interrupt pins, so decode this information. See
PCI-to-PCI Bridge spec r1.2, sec 3.2.5.17.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The Device name of a PCI or PCI Express device under OS may be exported via
ACPI _DSM function with function index 7.
This allows to connect a described PCI device in the platform documentation
or as labeled on the chassis with PCI devices shown via lspci.
The kernel already exports this string through sysfs under a PCI device through
the "label" sysfs attribute.
This patch reads the device name if available and shows it to the user.
Real world examples:
Device Name: "USB HS EHCI Controller #2 #3"
Device Name: "USB HS EHCI Controller #1"
Device Name: "SATA Controller #1"
Device Name: "Onboard LAN #1"
Device Name: "Onboard LAN #2"
Device Name: "Onboard Video (PILOT-3)"
Compare with PCI Firmware Spec v3.1 chapter 4.6.7 and
ACPI spec v5.0 chapter 9.14.1
The DeviceName is not shown by default, but starting from first verbose
parameter (-v).
V2: - Free label string if allocated
- Enhance changelog
Signed-off-by: Thomas Renninger <trenn@suse.de>
CC: linux-pci@vger.kernel.org
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This fixes building pciutils on Haiku.
Signed-off-by: François Revol <revol@free.fr>
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Thanks to John Spencer for bringing this to attention.
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Suggested by John Spencer.
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Patch by Robert Elliott from HP.
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Based on a patch by Zheng Huai Cheng <zhenghch@linux.vnet.ibm.com>.
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Per PCIe spec r3.0, Table 7-16, the Retrain Link bit is writable but
always returns 0 when read, so decoding it gives no useful information.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCIe spec (r3.0, Table 7-16) says the Read Completion Boundary is valid
for Root Ports, Endpoints, and Bridges. I only added decoding for PCIe-to-
PCI/PCI-X bridges because the RCB of a Bridge indicates the RCB of the
upstream Root Port, so I don't think it makes sense for PCI-to-PCIe
bridges.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCI_EXP_TYPE_PCI_BRIDGE type is a PCIe to PCI/PCI-X bridge, so be a bit
more complete in the comment and printed device type. Also, per PCIe spec
r3.0, Table 7-14, the PCIe Device Control "Bridge Configuration Retry
Enable" bit only applies to PCIe-to-PCI/PCI-X bridges; it does not apply to
PCI-to-PCIe bridges.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCIe Device Capabilities and Control bits related to Function
Level Reset are valid only for Endpoints, so only decode them in
that case.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCIe Device Capabilities "Endpoint L0s Acceptable Latency" and
"Endpoint L1 Acceptable Latency" are defined only for Endpoint functions,
so don't display them unless this is an endpoint.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCIe Link Capabilities "L0s Exit Latency" is the latency to exit
L0s, not L0, so label it "L0s" instead of "L0". This matches the
way we label the Device Capabilities "Endpoint L0s Acceptable Latency"
field as "Latency L0s". This also adds "Exit" to the description to
help distinguish it from the "Acceptable Latency" fields in the
Device Capabilities register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Root Complex Integrated Endpoints and Root Complex Event Collectors do not
have links and are not permitted to implement Link or Link 2 registers,
per PCIe spec r3.0, sec 1.3.2.3. Decoding them is useless and misleading.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Based on data contributed by David Box.
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Expose available L1 substate capabilities that can enable lower power
consumption when a PCIe Link is idle.
Signed-off-by: David Box <david.e.box@linux.intel.com>
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