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* Sylixos: READMEsylixosGongYuJian2018-03-201-0/+1
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* Sylixos: Bits of Makefile and configureGongYuJian2018-03-202-0/+5
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* lspci: fix printing DeviceNameViktor Prutyanov2018-03-201-1/+3
| | | | | | | | In commit ef6c9ec3a45992d9e7ef4716d444252baf2013e1 pci_fill_info() calls were moved and the label field is filled after its output. Before this patch lspci never prints 'DeviceName'. Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
* Sylixos: Trying to simplify probing mechanismMartin Mares2018-03-182-106/+6
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* Sylixos: Coding style cleanupMartin Mares2018-03-181-78/+45
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* Sylixos portMartin Mares2018-03-186-1/+309
| | | | Contributed by YuJian Gong.
* Introduced an explicit probe sequenceMartin Mares2018-03-172-15/+33
| | | | | | Previously, the probe order was determined by the order of back-ends. However, new back-ends must be always added at the end of the list to maintain ABI compatibility, so they were always probed last.
* Avoid "optarg" as an identifierMartin Mares2018-03-172-9/+9
| | | | On SylixOS, it is defined as a macro.
* Adjust prototypes of xmalloc(), xrealloc() and xstrdup()Martin Mares2018-03-172-10/+10
| | | | | | | SylixOS defines its own versions of these functions in its standard library, which collide with ours. However, their prototypes make more sense, because they follow the prototypes of the non-x versions in the C standard, so there is no harm in following them.
* lspci: Report if the PCIe link speed/width is full or downgradedMartin Mares2018-03-161-6/+22
| | | | Based on an idea by Dmitry Monakhov.
* lspci: Make DevCtl, DevSta, and AER decoding more consistentBjorn Helgaas2018-03-022-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change DevCtl error reporting enables so they match the corresponding DevSta bits: - DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- PCIe r4.0, sec 6.2.2, classifies errors as Correctable or Uncorrectable. Uncorrectable includes both Non-Fatal and Fatal errors. Decode the DevSta "Non-Fatal Error Detected" bit as "NonFatalErr", not "UncorrErr": - DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- + DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- Change the "Unsupported" and "UnsuppReq" labels in DevCtl and DevSta to match the "UnsupReq" used in AER. The Correctable error category doesn't include Non-Fatal errors, so change the AER Correctable Error Status "Advisory Non-Fatal Error Status" from "NonFatalErr" to "AdvNonFatalErr": - CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* fbsd-device should compile againMartin Mares2018-01-111-2/+2
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* fbsd-device: Hopefully fixed a bug in fbsd_scan()Martin Mares2017-12-311-1/+1
| | | | | | | The previous version was obviously wrong: as Andriy Gapon pointed out, we assign twice to t->dev, but never to t->func. Not tested, though, as I have no FreeBSD system at hand.
* lspci: Decode "VGA 16-bit decode" in bridge control registerBjorn Helgaas2017-12-313-1/+132
| | | | | | | | | Decode the "VGA 16-bit decode" bit in the bridge control register. This bit was added in the PCI-to-PCI Bridge Arch Spec, r1.2, sec 3.2.5.18. Note that the bit is only meaningful if the VGA Enable bit or the VGA Palette Snoop Enable bit is set. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* pciutils: Add the support for a DOS/DJGPP environmentRudolf Marek2017-12-3113-15/+154
| | | | | | | | | | | | | | | | | | | | | | | | Here is bit a blast from the past. The flashrom still supports the DOS/DJGPP environment, which requires pciutils to be compiled with DJGPP. I originally developed this patch in 2010, and I respun it for latest pciutils. * Add DJGPP as an OS target * Stop if endianess macros are not defined * Introduce new intel_io_lock/unclock function to synchronize I/O operations. There is a small issue left that "lspci" and "lspci.exe" are created. The ".exe" variants are not installed and also not cleaned. No idea if you want to fix that or not. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Compiled with: make ZLIB=no DNS=no HOST=i386-djgpp-djgpp CROSS_COMPILE=i586-pc-msdosdjgpp- \ PREFIX=/ DESTDIR=$PWD/../libpci-libgetopt \ STRIP="--strip-program=i586-pc-msdosdjgpp-strip -s" install install-lib If you put to C:\share\pci.ids file, the lspci.exe will also display the human readable output.
* README: kernel.org does not speak FTP any longerMartin Mares2017-11-191-1/+1
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* Forgot the ChangeLog for v3.5.6.v3.5.6Martin Mares2017-11-171-0/+11
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* Released as 3.5.6Martin Mares2017-11-172-3/+3
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* Updated pci.ids to today's snapshotMartin Mares2017-11-171-113/+509
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* pciutils: change MN VPD keyword to F_TEXTMartin Mares2017-11-171-1/+1
| | | | | | | | | The PCI spec defines all keyword data fields as ASCII unless otherwise noted. The MN keyword is not otherwise noted. To make the MN field human readable in lspci verbose outputs, this patch changes the MN keyword definition from F_BINARY to F_TEXT. Signed-off-by: John Walthour <return.0@me.com>
* fbsd-device: Use PCIOCGETCONF and PCIOCGETBAR when /dev/pci fd is readonly.Imre Vadász2017-11-171-8/+201
| | | | | | | | | This way we can at least fulfill some of the common requests without root privileges. This allows various applications (for example the google chrome webbrowser) to successfully probe the list of PCI devices without needing read-write access to the /dev/pci device file. Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
* fbsd-device: Make extended configuration space available.Imre Vadász2017-11-171-2/+2
| | | | Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
* fbsd-device: Fix fbsd-device backend on DragonFly BSD.Imre Vadász2017-11-171-2/+2
| | | | | | DragonFly also supports PCI domains same as FreeBSD. Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
* configure: use simpler/more portable echo_nMike Frysinger2017-11-171-6/+1
| | | | | The `echo -n` behavior is not in POSIX and not all shells support it. Use the portable `printf` func as defined by POSIX.
* Released as 3.5.5v3.5.5Martin Mares2017-07-053-3/+15
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* Updated pci.ids to today's snapshotMartin Mares2017-07-051-106/+355
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* lspci: Fix wrong read size for RootStaJeffy Chen2017-07-051-1/+1
| | | | | | | | | | | We are reading wrong size(word) for this cap, since: RootSta has: PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Fix "Auxiliary" spelling errorBjorn Helgaas2017-04-291-1/+1
| | | | Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Use #defines for greppabilityBjorn Helgaas2017-04-291-10/+10
| | | | | | | Use existing #defines when possible so grep/cscope/etc are more useful. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode only supported ASPM exit latenciesBjorn Helgaas2017-04-293-7/+343
| | | | | | | | | | | | | | | | | | | Per PCIe spec r3.1, sec 7.8.6, the L0s Exit Latency is only valid when L0s is supported, and similarly the L1 Exit Latency is only valid when L1 is supported. Only decode the L0s and L1 Exit Latencies if they are defined. For example, on a device that supports L1 but not L0s, the difference in the "lspci -vv" output looks like this: - LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us + LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us Correct the comments on the PCI_EXP_LNKCAP_L0S and PCI_EXP_LNKCAP_L1 definitions. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe BridgesBjorn Helgaas2017-04-292-1/+291
| | | | | | | | | | | | | | | | | The secondary side of a PCI/PCI-X to PCIe Bridge (a "reverse bridge") is a PCIe Downstream Port and could support a slot just like Root Ports and Switch Downstream Ports. Decode "Slot Implemented" for reverse bridges and, if true, the Slot Capabilities, Control, and Status registers. For a reverse bridge with no slot, the difference in the "lspci -vv" output looks like this: - Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge, MSI 00 + Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctlyBjorn Helgaas2017-04-292-2/+329
| | | | | | | | | | | | | | | | Indent the AtomicOpsCap and AtomicOpsCtl fields to make it clear that these are part of the DevCap2 and DevCtl2 registers. The difference in the "lspci -vv" output looks like this: DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ - AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- + AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- - AtomicOpsCtl: ReqEn- EgressBlck- + AtomicOpsCtl: ReqEn- EgressBlck- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Include "ECRC" in the ECRC generate/check labelsBjorn Helgaas2017-04-292-1/+328
| | | | | | | | | | | Include "ECRC" in the ECRC generate/check labels. The difference in the "lspci -vv" output looks like this: - AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode AER Root Error Command, Root Error Status, Error SourceBjorn Helgaas2017-04-295-12/+682
| | | | | | | | | | | | | | | | | | Decode the AER Root Error Command, Root Error Status, and Error Source Identification registers. Per PCIe r3.1, sec 7.10, these registers are only available for Root Ports and Root Complex Event Collectors, so we have to check the Device/Port Type from the PCIe capability. The difference in the "lspci -vv" output looks like this (for a Root Port): + RootCmd: CERptEn- NFERptEn- FERptEn- + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Dump AER Header LogBjorn Helgaas2017-04-292-2/+331
| | | | | | | | | | | | | Dump the AER Header Log register. This contains the header for the TLP corresponding to a detected error. It's probably beyond the scope of lspci to decode the header itself, but it's interesting to at least show the data as a hint for human readers. The difference in the "lspci -vv" output looks like this: + HeaderLog: 00000000 00000000 00000000 00000000 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode AER Multiple Header and TLP Prefix Log bitsBjorn Helgaas2017-04-293-3/+331
| | | | | | | | | | | | | Decode the AER Multiple Header Recording and TLP Prefix Log Present bits in the AER Capabilities and Control register. The difference in the "lspci -vv" output looks like this: - AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Released as 3.5.4v3.5.4Martin Mares2017-02-264-4/+11
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* types.h: Provide u64 on all systemsMartin Mares2017-02-242-8/+18
| | | | | Recent changes in lspci.c require u64 to be present regardless of PCI_HAVE_64BIT_ADDRESS.
* Released as 3.5.3v3.5.3Martin Mares2017-02-153-5/+23
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* Updated pci.ids to today's snapshotMartin Mares2017-02-151-120/+479
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* ls-caps: Minor cleanup of cap_express_dev2()Martin Mares2017-02-151-2/+1
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* pciutils: Add test case for pci atomic opsSatanand Burla2017-02-151-0/+54
| | | | | | This patch adds test case for atomic ops Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com>
* pciutils: Add decode for Atomic Ops in lspciSatanand Burla2017-02-152-0/+53
| | | | | | | This adds support for decoding Atomic ops added in ECN https://pcisig.com/sites/default/files/specification_documents/ECN_Atomic_Ops_080417.pdf Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com>
* lspci: Support GEN4 speed (16GT/s)Gavin Shan2017-02-151-0/+4
| | | | | | | | | This enables "lspci" to show GEN4 speed (16GT/s) properly according to the contents in register PCI_EXP_LNKCAP, PCI_EXP_LNKSTA and PCI_EXP_LNKCTL2. Reported-by: Carol Soto <clsoto@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
* lspci: better display of ranges behind a bridgeMartin Mares2016-12-311-18/+36
| | | | | | | | | | | | | When the range is non-empty, it is always printed together with its size. If it is empty, the output depends on the verbosity level chosen: - no verbosity: nothing is printed - -vvv: full range is printed - anything between: "none" is printed Thanks to Harry Mallon and Bjorn Helgaas for inspiration.
* ls-kernel: use libkmod's default to find modulesVladimír Čunát2016-12-311-7/+1
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* Released as 3.5.2v3.5.2Martin Mares2016-10-033-3/+13
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* Updated pci.ids to today's snapshotMartin Mares2016-10-031-120/+620
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* Merge branch 'l1pm'Martin Mares2016-10-033-53/+377
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| * pciutils: Update the tests/cap-l1-pm with actual device dataRajat Jain2016-10-031-24/+303
| | | | | | | | | | | | | | Update the test data using lspci output taken from a card that supports L1 PM supstates. Signed-off-by: Rajat Jain <rajatja@google.com>
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