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-rw-r--r--Makefile17
-rw-r--r--lib/Makefile6
-rw-r--r--lib/header.h80
-rw-r--r--lib/i386-io-linux.h48
-rw-r--r--lib/i386-io-windows.h3
-rw-r--r--lib/i386-ports.c20
-rw-r--r--lib/win32-cfgmgr32.c18
-rw-r--r--lib/winrsrc.rc.in (renamed from lib/dllrsrc.rc.in)12
-rw-r--r--ls-ecaps.c227
-rw-r--r--tests/cap-dvsec-cxl258
10 files changed, 662 insertions, 27 deletions
diff --git a/Makefile b/Makefile
index e2e3bd7..11f15f1 100644
--- a/Makefile
+++ b/Makefile
@@ -112,6 +112,21 @@ example.o: example.c $(PCIINC)
%$(EXEEXT): %.o
$(CC) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o $@
+ifdef PCI_OS_WINDOWS
+comma := ,
+%-rsrc.rc: lib/winrsrc.rc.in
+ sed <$< >$@ -e 's,@PCILIB_VERSION@,$(PCILIB_VERSION),' \
+ -e 's,@PCILIB_VERSION_WINRC@,$(subst .,\$(comma),$(PCILIB_VERSION).0),' \
+ -e 's,@FILENAME@,$(subst -rsrc.rc,$(EXEEXT),$@),' \
+ -e 's,@DESCRIPTION@,$(subst -rsrc.rc,,$@),' \
+ -e 's,@LIBRARY_BUILD@,0,' \
+ -e 's,@DEBUG_BUILD@,$(if $(findstring -g,$(CFLAGS)),1,0),'
+%-rsrc.o: %-rsrc.rc
+ $(WINDRES) --input=$< --output=$@ --input-format=rc --output-format=coff
+lspci$(EXEEXT): lspci-rsrc.o
+setpci$(EXEEXT): setpci-rsrc.o
+endif
+
%.8 %.7 %.5: %.man
M=`echo $(DATE) | sed 's/-01-/-January-/;s/-02-/-February-/;s/-03-/-March-/;s/-04-/-April-/;s/-05-/-May-/;s/-06-/-June-/;s/-07-/-July-/;s/-08-/-August-/;s/-09-/-September-/;s/-10-/-October-/;s/-11-/-November-/;s/-12-/-December-/;s/\(.*\)-\(.*\)-\(.*\)/\3 \2 \1/'` ; sed <$< >$@ "s/@TODAY@/$$M/;s/@VERSION@/pciutils-$(VERSION)/;s#@IDSDIR@#$(IDSDIR)#;s#@PCI_IDS@#$(PCI_IDS)#"
@@ -125,7 +140,7 @@ TAGS:
clean:
rm -f `find . -name "*~" -o -name "*.[oa]" -o -name "\#*\#" -o -name TAGS -o -name core -o -name "*.orig"`
- rm -f update-pciids lspci$(EXEEXT) setpci$(EXEEXT) example$(EXEEXT) lib/config.* *.[578] pci.ids.gz lib/*.pc lib/*.so lib/*.so.* lib/*.dll lib/*.def lib/dllrsrc.rc tags
+ rm -f update-pciids lspci$(EXEEXT) setpci$(EXEEXT) example$(EXEEXT) lib/config.* *.[578] pci.ids.gz lib/*.pc lib/*.so lib/*.so.* lib/*.dll lib/*.def lib/dllrsrc.rc *-rsrc.rc tags
rm -rf maint/dist
distclean: clean
diff --git a/lib/Makefile b/lib/Makefile
index a119bdf..76ef0d4 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -83,10 +83,12 @@ $(PCIIMPDEF): libpci.ver ver2def.pl
$(PCIIMPLIB): $(PCIIMPDEF)
$(DLLTOOL) --input-def $< --output-lib $@
comma := ,
-dllrsrc.rc: dllrsrc.rc.in
+dllrsrc.rc: winrsrc.rc.in
sed <$< >$@ -e 's,@PCILIB_VERSION@,$(PCILIB_VERSION),' \
-e 's,@PCILIB_VERSION_WINRC@,$(subst .,\$(comma),$(PCILIB_VERSION).0),' \
- -e 's,@PCILIB@,$(PCILIB),' \
+ -e 's,@FILENAME@,$(PCILIB),' \
+ -e 's,@DESCRIPTION@,libpci,' \
+ -e 's,@LIBRARY_BUILD@,1,' \
-e 's,@DEBUG_BUILD@,$(if $(findstring -g,$(CFLAGS)),1,0),'
dllrsrc.o: dllrsrc.rc
$(WINDRES) --input=$< --output=$@ --input-format=rc --output-format=coff
diff --git a/lib/header.h b/lib/header.h
index e74f6d8..63ee03c 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1129,6 +1129,86 @@
/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */
#define PCI_CXL_RL_BLOCK1_LO 0x0c
+/* PCIe CXL Designated Vendor-Specific Capabilities for Global Persistent Flush */
+#define PCI_CXL_GPF_DEV_LEN 0x10
+#define PCI_CXL_GPF_DEV_PHASE2_DUR 0x0a /* GPF Phase 2 Duration Register */
+#define PCI_CXL_GPF_DEV_PHASE2_POW 0x0c /* GPF Phase 2 Power Register */
+#define PCI_CXL_GPF_DEV_1US 0x0
+#define PCI_CXL_GPF_DEV_10US 0x1
+#define PCI_CXL_GPF_DEV_100US 0x2
+#define PCI_CXL_GPF_DEV_1MS 0x3
+#define PCI_CXL_GPF_DEV_10MS 0x4
+#define PCI_CXL_GPF_DEV_100MS 0x5
+#define PCI_CXL_GPF_DEV_1S 0x6
+#define PCI_CXL_GPF_DEV_10S 0x7
+#define PCI_CXL_GPF_PORT_LEN 0x10
+#define PCI_CXL_GPF_PORT_PHASE1_CTRL 0x0c /* GPF Phase 1 Control Register */
+#define PCI_CXL_GPF_PORT_PHASE2_CTRL 0x0e /* GPF Phase 2 Control Register */
+#define PCI_CXL_GPF_PORT_1US 0x0
+#define PCI_CXL_GPF_PORT_10US 0x1
+#define PCI_CXL_GPF_PORT_100US 0x2
+#define PCI_CXL_GPF_PORT_1MS 0x3
+#define PCI_CXL_GPF_PORT_10MS 0x4
+#define PCI_CXL_GPF_PORT_100MS 0x5
+#define PCI_CXL_GPF_PORT_1S 0x6
+#define PCI_CXL_GPF_PORT_10S 0x7
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
+#define PCI_CXL_FB_LEN 0x20
+#define PCI_CXL_FB_PORT_CAP 0x0a /* CXL Flex Bus Port Capability Register */
+#define PCI_CXL_FB_CAP_CACHE 0x0001 /* CXL.cache Capable */
+#define PCI_CXL_FB_CAP_IO 0x0002 /* CXL.io Capable */
+#define PCI_CXL_FB_CAP_MEM 0x0004 /* CXL.mem Capable */
+#define PCI_CXL_FB_CAP_68B_FLIT 0x0020 /* CXL 68B Flit and VH Capable */
+#define PCI_CXL_FB_CAP_MULT_LOG_DEV 0x0040 /* CXL Multi-Logical Device Capable */
+#define PCI_CXL_FB_CAP_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Capable */
+#define PCI_CXL_FB_CAP_PBR_FLIT 0x4000 /* CXL PBR Flit Capable */
+#define PCI_CXL_FB_PORT_CTRL 0x0c /* CXL Flex Bus Port Control Register */
+#define PCI_CXL_FB_CTRL_CACHE 0x0001 /* CXL.cache Enable */
+#define PCI_CXL_FB_CTRL_IO 0x0002 /* CXL.io Enable */
+#define PCI_CXL_FB_CTRL_MEM 0x0004 /* CXL.mem Enable */
+#define PCI_CXL_FB_CTRL_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enable */
+#define PCI_CXL_FB_CTRL_DRFT_BUF 0x0010 /* Drift Buffer Enable */
+#define PCI_CXL_FB_CTRL_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enable */
+#define PCI_CXL_FB_CTRL_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enable */
+#define PCI_CXL_FB_CTRL_RCD 0x0080 /* Disable RCD Training */
+#define PCI_CXL_FB_CTRL_RETIMER1 0x0100 /* Retimer1 Present */
+#define PCI_CXL_FB_CTRL_RETIMER2 0x0200 /* Retimer2 Present */
+#define PCI_CXL_FB_CTRL_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enable */
+#define PCI_CXL_FB_CTRL_PBR_FLIT 0x4000 /* CXL PBR Flit Enable */
+#define PCI_CXL_FB_PORT_STATUS 0x0e /* CXL Flex Bus Port Status Register */
+#define PCI_CXL_FB_STAT_CACHE 0x0001 /* CXL.cache Enabled */
+#define PCI_CXL_FB_STAT_IO 0x0002 /* CXL.io Enabled */
+#define PCI_CXL_FB_STAT_MEM 0x0004 /* CXL.mem Enabled */
+#define PCI_CXL_FB_STAT_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enabled */
+#define PCI_CXL_FB_STAT_DRFT_BUF 0x0010 /* Drift Buffer Enabled */
+#define PCI_CXL_FB_STAT_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enabled */
+#define PCI_CXL_FB_STAT_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enabled */
+#define PCI_CXL_FB_STAT_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enabled */
+#define PCI_CXL_FB_STAT_PBR_FLIT 0x4000 /* CXL PBR Flit Enabled */
+#define PCI_CXL_FB_MOD_TS_DATA 0x10 /* CXL Flex Bus Port Received Modified TS Data Phase1 Register */
+#define PCI_CXL_FB_PORT_CAP2 0x14 /* CXL Flex Bus Port Capability2 Register */
+#define PCI_CXL_FB_CAP2_NOP_HINT 0x01 /* NOP Hint Capable */
+#define PCI_CXL_FB_PORT_CTRL2 0x18 /* CXL Flex Bus Port Control2 Register */
+#define PCI_CXL_FB_CTRL2_NOP_HINT 0x01 /* NOP Hint Enable */
+#define PCI_CXL_FB_PORT_STATUS2 0x1c /* CXL Flex Bus Port Status2 Register */
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
+#define PCI_CXL_MLD_LEN 0x10
+#define PCI_CXL_MLD_NUM_LD 0xa
+#define PCI_CXL_MLD_MAX_LD 0x10
+
+/* PCIe CXL Designated Vendor-Specific Capabilities for Non-CXL Function Map */
+#define PCI_CXL_FUN_MAP_LEN 0x2c
+#define PCI_CXL_FUN_MAP_REG_0 0x0c
+#define PCI_CXL_FUN_MAP_REG_1 0x10
+#define PCI_CXL_FUN_MAP_REG_2 0x14
+#define PCI_CXL_FUN_MAP_REG_3 0x18
+#define PCI_CXL_FUN_MAP_REG_4 0x1c
+#define PCI_CXL_FUN_MAP_REG_5 0x20
+#define PCI_CXL_FUN_MAP_REG_6 0x24
+#define PCI_CXL_FUN_MAP_REG_7 0x28
+
/* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
diff --git a/lib/i386-io-linux.h b/lib/i386-io-linux.h
index 731e8e3..a2fd69e 100644
--- a/lib/i386-io-linux.h
+++ b/lib/i386-io-linux.h
@@ -7,17 +7,61 @@
*/
#include <sys/io.h>
+#include <errno.h>
+
+static int ioperm_enabled;
+static int iopl_enabled;
static int
intel_setup_io(struct pci_access *a UNUSED)
{
- return (iopl(3) < 0) ? 0 : 1;
+ if (ioperm_enabled || iopl_enabled)
+ return 1;
+
+ /*
+ * Before Linux 2.6.8, only the first 0x3ff I/O ports permissions can be
+ * modified via ioperm(). Since 2.6.8 all ports are supported.
+ * Since Linux 5.5, EFLAGS-based iopl() implementation was removed and
+ * replaced by new TSS-IOPB-map-all-based emulator. Before Linux 5.5,
+ * EFLAGS-based iopl() allowed userspace to enable/disable interrupts,
+ * which is dangerous. So prefer usage of ioperm() and fallback to iopl().
+ */
+ if (ioperm(0xcf8, 8, 1) < 0) /* conf1 + conf2 ports */
+ {
+ if (errno == EINVAL) /* ioperm() unsupported */
+ {
+ if (iopl(3) < 0)
+ return 0;
+ iopl_enabled = 1;
+ return 1;
+ }
+ return 0;
+ }
+ if (ioperm(0xc000, 0xfff, 1) < 0) /* remaining conf2 ports */
+ {
+ ioperm(0xcf8, 8, 0);
+ return 0;
+ }
+
+ ioperm_enabled = 1;
+ return 1;
}
static inline void
intel_cleanup_io(struct pci_access *a UNUSED)
{
- iopl(0);
+ if (ioperm_enabled)
+ {
+ ioperm(0xcf8, 8, 0);
+ ioperm(0xc000, 0xfff, 0);
+ ioperm_enabled = 0;
+ }
+
+ if (iopl_enabled)
+ {
+ iopl(0);
+ iopl_enabled = 0;
+ }
}
static inline void intel_io_lock(void)
diff --git a/lib/i386-io-windows.h b/lib/i386-io-windows.h
index 1509d7d..6bb578c 100644
--- a/lib/i386-io-windows.h
+++ b/lib/i386-io-windows.h
@@ -1343,7 +1343,8 @@ intel_setup_io(struct pci_access *a)
/* On NT-based systems issue ProcessUserModeIOPL syscall which changes IOPL to 3. */
if (!SetProcessUserModeIOPL())
{
- a->warning("NT ProcessUserModeIOPL call failed with error: %lu.", (unsigned long int)GetLastError());
+ DWORD error = GetLastError();
+ a->debug("NT ProcessUserModeIOPL call failed: %s.", error == ERROR_INVALID_FUNCTION ? "Not Implemented" : error == ERROR_PRIVILEGE_NOT_HELD ? "Access Denied" : "Operation Failed");
return 0;
}
diff --git a/lib/i386-ports.c b/lib/i386-ports.c
index 2e64fe4..0ca87dd 100644
--- a/lib/i386-ports.c
+++ b/lib/i386-ports.c
@@ -136,6 +136,9 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
if (d->domain || pos >= 256)
return 0;
+ if (len != 1 && len != 2 && len != 4)
+ return pci_generic_block_read(d, pos, buf, len);
+
intel_io_lock();
outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
@@ -150,8 +153,6 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
case 4:
((u32 *) buf)[0] = cpu_to_le32(inl(addr));
break;
- default:
- res = pci_generic_block_read(d, pos, buf, len);
}
intel_io_unlock();
@@ -167,6 +168,9 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
if (d->domain || pos >= 256)
return 0;
+ if (len != 1 && len != 2 && len != 4)
+ return pci_generic_block_write(d, pos, buf, len);
+
intel_io_lock();
outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
@@ -181,8 +185,6 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
case 4:
outl(le32_to_cpu(((u32 *) buf)[0]), addr);
break;
- default:
- res = pci_generic_block_write(d, pos, buf, len);
}
intel_io_unlock();
return res;
@@ -228,6 +230,9 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
/* conf2 supports only 16 devices per bus */
return 0;
+ if (len != 1 && len != 2 && len != 4)
+ return pci_generic_block_read(d, pos, buf, len);
+
intel_io_lock();
outb((d->func << 1) | 0xf0, 0xcf8);
outb(d->bus, 0xcfa);
@@ -242,8 +247,6 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
case 4:
((u32 *) buf)[0] = cpu_to_le32(inl(addr));
break;
- default:
- res = pci_generic_block_read(d, pos, buf, len);
}
outb(0, 0xcf8);
intel_io_unlock();
@@ -263,6 +266,9 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
/* conf2 supports only 16 devices per bus */
return 0;
+ if (len != 1 && len != 2 && len != 4)
+ return pci_generic_block_write(d, pos, buf, len);
+
intel_io_lock();
outb((d->func << 1) | 0xf0, 0xcf8);
outb(d->bus, 0xcfa);
@@ -277,8 +283,6 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
case 4:
outl(le32_to_cpu(* (u32 *) buf), addr);
break;
- default:
- res = pci_generic_block_write(d, pos, buf, len);
}
outb(0, 0xcf8);
diff --git a/lib/win32-cfgmgr32.c b/lib/win32-cfgmgr32.c
index 004f95f..a3404d1 100644
--- a/lib/win32-cfgmgr32.c
+++ b/lib/win32-cfgmgr32.c
@@ -126,7 +126,7 @@ resolve_cfgmgr32_functions(void)
* cfgmgr32.dll uses custom non-Win32 error numbers which are unsupported by
* Win32 APIs like GetLastError() and FormatMessage() functions.
*
- * Windows 7 instroduced new cfgmgr32.dll function CM_MapCrToWin32Err() for
+ * Windows 7 introduced new cfgmgr32.dll function CM_MapCrToWin32Err() for
* translating mapping CR_* errors to Win32 errors but most error codes are
* not mapped. So this function is unusable.
*
@@ -498,18 +498,28 @@ retry_service_config:
service_image_path[systemroot_len++] = L'\\';
wcscpy(service_image_path + systemroot_len, service_config->lpBinaryPathName + sizeof("\\SystemRoot\\")-1);
}
- else if (wcsncmp(service_config->lpBinaryPathName, L"\\??\\UNC\\", sizeof("\\??\\UNC\\")-1) == 0)
+ else if (wcsncmp(service_config->lpBinaryPathName, L"\\??\\UNC\\", sizeof("\\??\\UNC\\")-1) == 0 ||
+ wcsncmp(service_config->lpBinaryPathName, L"\\??\\\\UNC\\", sizeof("\\??\\\\UNC\\")-1) == 0)
{
/* ImagePath is in NT UNC namespace, convert to Win32 UNC path via "\\\\" prefix. */
service_image_path = pci_malloc(a, sizeof(WCHAR) * (sizeof("\\\\") + wcslen(service_config->lpBinaryPathName) - (sizeof("\\??\\UNC\\")-1)));
+ /* Namespace separator may be single or double backslash. */
+ driver_path_len = sizeof("\\??\\")-1;
+ if (service_config->lpBinaryPathName[driver_path_len] == L'\\')
+ driver_path_len++;
+ driver_path_len += sizeof("UNC\\")-1;
wcscpy(service_image_path, L"\\\\");
- wcscpy(service_image_path + sizeof("\\\\")-1, service_config->lpBinaryPathName + sizeof("\\??\\UNC\\")-1);
+ wcscpy(service_image_path + sizeof("\\\\")-1, service_config->lpBinaryPathName + driver_path_len);
}
else if (wcsncmp(service_config->lpBinaryPathName, L"\\??\\", sizeof("\\??\\")-1) == 0)
{
/* ImagePath is in NT Global?? namespace, root of the Win32 file namespace, so just remove "\\??\\" prefix to get Win32 path. */
service_image_path = pci_malloc(a, sizeof(WCHAR) * (wcslen(service_config->lpBinaryPathName) - (sizeof("\\??\\")-1)));
- wcscpy(service_image_path, service_config->lpBinaryPathName + sizeof("\\??\\")-1);
+ /* Namespace separator may be single or double backslash. */
+ driver_path_len = sizeof("\\??\\")-1;
+ if (service_config->lpBinaryPathName[driver_path_len] == L'\\')
+ driver_path_len++;
+ wcscpy(service_image_path, service_config->lpBinaryPathName + driver_path_len);
}
else if (service_config->lpBinaryPathName[0] != L'\\')
{
diff --git a/lib/dllrsrc.rc.in b/lib/winrsrc.rc.in
index 519772b..e061bff 100644
--- a/lib/dllrsrc.rc.in
+++ b/lib/winrsrc.rc.in
@@ -9,7 +9,11 @@ FILEFLAGS VS_FF_DEBUG
FILEFLAGS 0
#endif
FILEOS VOS_NT_WINDOWS32
+#if @LIBRARY_BUILD@
FILETYPE VFT_DLL
+#else
+FILETYPE VFT_APP
+#endif
FILESUBTYPE 0
BEGIN
BLOCK "StringFileInfo"
@@ -20,16 +24,16 @@ BEGIN
*/
BLOCK "040904B0" /* Default U.S. English language, UNICODE/UTF-16 codepage */
BEGIN
- VALUE "FileDescription", "libpci"
+ VALUE "FileDescription", "@DESCRIPTION@"
VALUE "FileVersion", "@PCILIB_VERSION@"
- VALUE "InternalName", "@PCILIB@"
- VALUE "OriginalFilename", "@PCILIB@"
+ VALUE "InternalName", "@FILENAME@"
+ VALUE "OriginalFilename", "@FILENAME@"
VALUE "ProductName", "pciutils"
VALUE "ProductVersion", "@PCILIB_VERSION@"
END
END
BLOCK "VarFileInfo"
BEGIN
- VALUE "Translation", 0x0409, 0x004B0 /* Default U.S. English language, UNICODE/UTF-16 codepage */
+ VALUE "Translation", 0x0409, 0x04B0 /* Default U.S. English language, UNICODE/UTF-16 codepage */
END
END
diff --git a/ls-ecaps.c b/ls-ecaps.c
index b9a4512..df41626 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -839,6 +839,223 @@ dvsec_cxl_register_locator(struct device *d, int where, int len)
}
static void
+dvsec_cxl_gpf_device(struct device *d, int where)
+{
+ u32 l;
+ u16 w, duration;
+ u8 time_base, time_scale;
+
+ w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
+ time_base = BITS(w, 0, 4);
+ time_scale = BITS(w, 8, 4);
+
+ switch (time_scale)
+ {
+ case PCI_CXL_GPF_DEV_100US:
+ case PCI_CXL_GPF_DEV_100MS:
+ duration = time_base * 100;
+ break;
+ case PCI_CXL_GPF_DEV_10US:
+ case PCI_CXL_GPF_DEV_10MS:
+ case PCI_CXL_GPF_DEV_10S:
+ duration = time_base * 10;
+ break;
+ case PCI_CXL_GPF_DEV_1US:
+ case PCI_CXL_GPF_DEV_1MS:
+ case PCI_CXL_GPF_DEV_1S:
+ duration = time_base;
+ break;
+ default:
+ /* Reserved */
+ printf("\t\tReserved time scale encoding %x\n", time_scale);
+ duration = time_base;
+ }
+
+ printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
+ (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
+ (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
+ (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
+
+ l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
+ printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
+}
+
+static void
+dvsec_cxl_gpf_port(struct device *d, int where)
+{
+ u16 w, timeout;
+ u8 time_base, time_scale;
+
+ w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
+ time_base = BITS(w, 0, 4);
+ time_scale = BITS(w, 8, 4);
+
+ switch (time_scale)
+ {
+ case PCI_CXL_GPF_PORT_100US:
+ case PCI_CXL_GPF_PORT_100MS:
+ timeout = time_base * 100;
+ break;
+ case PCI_CXL_GPF_PORT_10US:
+ case PCI_CXL_GPF_PORT_10MS:
+ case PCI_CXL_GPF_PORT_10S:
+ timeout = time_base * 10;
+ break;
+ case PCI_CXL_GPF_PORT_1US:
+ case PCI_CXL_GPF_PORT_1MS:
+ case PCI_CXL_GPF_PORT_1S:
+ timeout = time_base;
+ break;
+ default:
+ /* Reserved */
+ printf("\t\tReserved time scale encoding %x\n", time_scale);
+ timeout = time_base;
+ }
+
+ printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
+ (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
+ (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
+ (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+
+ w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
+ time_base = BITS(w, 0, 4);
+ time_scale = BITS(w, 8, 4);
+
+ switch (time_scale)
+ {
+ case PCI_CXL_GPF_PORT_100US:
+ case PCI_CXL_GPF_PORT_100MS:
+ timeout = time_base * 100;
+ break;
+ case PCI_CXL_GPF_PORT_10US:
+ case PCI_CXL_GPF_PORT_10MS:
+ case PCI_CXL_GPF_PORT_10S:
+ timeout = time_base * 10;
+ break;
+ case PCI_CXL_GPF_PORT_1US:
+ case PCI_CXL_GPF_PORT_1MS:
+ case PCI_CXL_GPF_PORT_1S:
+ timeout = time_base;
+ break;
+ default:
+ /* Reserved */
+ printf("\t\tReserved time scale encoding %x\n", time_scale);
+ timeout = time_base;
+ }
+
+ printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
+ (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
+ (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
+ (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+}
+
+static void
+dvsec_cxl_flex_bus(struct device *d, int where, int rev)
+{
+ u16 w;
+ u32 l, data;
+
+ if (rev < 1)
+ {
+ printf("\t\tRevision %d not supported\n", rev);
+ return;
+ }
+
+ w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
+ printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
+ FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
+ FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
+ FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
+
+ if (rev > 1)
+ printf(" 256BFlit%c PBRFlit%c",
+ FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
+
+ w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
+ printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
+ FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
+ FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
+ FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
+ FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
+ FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
+
+ if (rev > 1)
+ printf(" 256BFlit%c PBRFlit%c",
+ FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
+
+ w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
+ printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
+ FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
+ FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
+ FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
+ FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
+
+ if (rev > 1)
+ printf(" 256BFlit%c PBRFlit%c",
+ FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
+
+ l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
+ data = BITS(l, 0, 24);
+ printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
+
+ if (rev > 1)
+ {
+ u8 nop;
+
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
+ printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
+
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
+ printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
+
+ l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
+ nop = BITS(l, 0, 2);
+ printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
+ }
+}
+
+static void
+dvsec_cxl_mld(struct device *d, int where)
+{
+ u16 w;
+
+ w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
+
+ /* Encodings greater than 16 are reserved */
+ if (w && w <= PCI_CXL_MLD_MAX_LD)
+ printf("\t\tNumLogDevs: %d\n", w);
+}
+
+static void
+dvsec_cxl_function_map(struct device *d, int where)
+{
+
+ printf("\t\tFuncMap 0: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
+
+ printf("\t\tFuncMap 1: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
+
+ printf("\t\tFuncMap 2: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
+
+ printf("\t\tFuncMap 3: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
+
+ printf("\t\tFuncMap 4: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
+
+ printf("\t\tFuncMap 5: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
+
+ printf("\t\tFuncMap 6: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
+
+ printf("\t\tFuncMap 7: %08x\n",
+ (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
+}
+
+static void
cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
{
printf(": CXL\n");
@@ -854,25 +1071,25 @@ cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
dvsec_cxl_device(d, rev, where, len);
break;
case 2:
- printf("\t\tNon-CXL Function Map DVSEC\n");
+ dvsec_cxl_function_map(d, where);
break;
case 3:
dvsec_cxl_port(d, where, len);
break;
case 4:
- printf("\t\tGPF DVSEC for Port\n");
+ dvsec_cxl_gpf_port(d, where);
break;
case 5:
- printf("\t\tGPF DVSEC for Device\n");
+ dvsec_cxl_gpf_device(d, where);
break;
case 7:
- printf("\t\tPCIe DVSEC Flex Bus Port\n");
+ dvsec_cxl_flex_bus(d, where, rev);
break;
case 8:
dvsec_cxl_register_locator(d, where, len);
break;
case 9:
- printf("\t\tMLD DVSEC\n");
+ dvsec_cxl_mld(d, where);
break;
default:
printf("\t\tUnknown ID %04x\n", id);
diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
index a24e3fb..c5fa9e7 100644
--- a/tests/cap-dvsec-cxl
+++ b/tests/cap-dvsec-cxl
@@ -351,3 +351,261 @@ fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+7f:00.0 CXL: Xilinx Corporation Device c084 (rev 70) (prog-if 10 [CXL Memory Device (CXL 2.x)])
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