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| author | Bjorn Helgaas <bhelgaas@google.com> | 2015-12-10 13:50:01 -0600 |
|---|---|---|
| committer | Martin Mares <mj@ucw.cz> | 2015-12-22 16:35:24 +0100 |
| commit | acf56dd28df9d265a421b0207516134b99237fcc (patch) | |
| tree | 01cad3a095e2c3c672a09dcb61959b7dcdb10016 | |
| parent | bfd8658f27401837d79d7d3310962f7dc2444d34 (diff) | |
| download | pciutils-acf56dd28df9d265a421b0207516134b99237fcc.tar.gz | |
lspci: Decode DevCap SlotPowerLimit for all components with Upstream Ports
The SlotPowerLimit in the Slot Capability indicates how much power the slot
can supply to a downstream device. A Root Port or Switch Downstream Port
communicates the limit via a Set_Slot_Power_Limit Message on the link. The
component on the other end of the link copies the limit from the message to
the Captured Slot Power Limit in its Device Capability [see PCIe r3.0, sec
2.2.8.5].
The Captured SlotPowerLimit is relevant for all devices on the downstream
end of a Link. This includes Endpoints and Bridges as well as
Switch Upstream Ports.
Decode the DevCap Captured SlotPowerLimit for Endpoints and Bridges as well
as Switch Upstream Ports.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| -rw-r--r-- | ls-caps.c | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -678,7 +678,8 @@ static void cap_express_dev(struct device *d, int where, int type) if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) printf(" FLReset%c", FLAG(t, PCI_EXP_DEVCAP_FLRESET)); - if (type == PCI_EXP_TYPE_UPSTREAM) + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || + (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" SlotPowerLimit %.3fW", power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); |