| Commit message (Collapse) | Author | Age | Files | Lines |
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Now reduce the effect as the bitrate goes up and don't boost already-boosted
transients.
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The idea is to allow more noise than the default in quiet segments.
Right now, this hurts for high bitrates and would need to be disabled.
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Does not change the behaviour of the VBR code in most cases. The only
exception is that the VBR offset is now taken into accound in the base_rate,
which will have a (very minor) impact on CVBR at low rate.
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These were probably cribbed from libogg, but we don't use them here,
opus_types.h instead has a list of hardcoded arch definitions.
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The loop no longer reads past its buffer and is slightly faster.
Also fixes RESTORE_STACK in celt_iir().
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There's no CPU detection for it, it only gets enabled by __SSE__
which gcc (other compilers?) defines automatically when supported
by -march=, which means at least all x86-64. For ia32, the user needs to
enable it in the CFLAGS.
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Run-time CPU detection (RTCD) is enabled by default if target platform support
it.
It can be disable at compile time with --disable-rtcd option.
Add RTCD support for ARM architecture.
Thanks to Timothy B. Terriberry for help and code review
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
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With gcc-4.4 at least, the raw asm.s files will always successfully
compile even if the default -march for the compiler would not support
those instructions. So switch to testing the inline asm versions,
where the compiler will barf if they aren't supported by the default
arch if no -march is explicitly given, or if they aren't supported by
the requested -march when it is.
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If opus_compare doesn't exist or isn't executable, tests failed normally
which could be misleading.
So test for existence and mode to avoid this ambiguity.
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Using a sliding window to pre-compute all yy values.
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Again, this only impacts the PLC and we assume the order is a multiple of 4.
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Only impacts the PLC. We now assume that the order is a multiple of 4.
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Rename y0 and y1 because of the name clash with Bessel functions.
Initialize y_3 to zero because gcc is too dumb to realize it can't
be used uninitialized.
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Computes most of the auto-correlation by reusing pitch_xcorr(). We only
need lag*(lag-1)/2 MACs to complete the calculations.
To do this, pitch_xcorr() was modified so that it no longer truncates the
length to a multiple of 4. Also, the xcorr didn't need the floor at -1.
As a side benefit, this speeds up the PLC, which uses a higher order LPC
filter.
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Also creates a new hardcoded 5th order fir.
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If there's no complete author tag, we need to add an opening
quote character manually. See the EBU entry.
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The normative reference is now the channel configurations
give directly in the draft.
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Previous markup was invalid.
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I've done some editing for clarity, but more needs to be done.
The language needs clean-up, we should forward-reference the LPC
Extrapolation section, and we need a reference for actually
computing linear prediction coefficients.
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More recent versions of draft-sheffer-running-code suggest referring
to a wiki. We'd like to try maintaining the implementation status
separately.
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About 30% faster on x86.
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Introduced in c152d602.
Thanks to Pedro Becerra for the report.
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Introduced in c152d602.
Thanks to Pedro Becerra for the report.
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Thanks to John Ridges for the report.
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Define ARMv4_ASM to 1 like the other ARM defines.
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Remove a redundant include and some dead stores.
Patch by Aurélien Zanelli <aurelien.zanelli@parrot.com>.
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Measures a 0.1% speedup on 96 kbps stereo encode+decode on a
Cortex A8.
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Reorder register usage to take advantage of early termination on
multiplications and reorder a load instruction to hide its
latency on ARM9.
Speeds up decoding of a 64 kbps test file by 0.1MHz on an ARM7TDMI
and 0.2MHz on an ARM9TDMI.
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
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Uses a C implementation with a 32*32 => 64 multiplication, which
ARM has.
Speeds up decoding of a 64 kbps test file by 0.5MHz on an ARM7TDMI
and 1.0MHz on an ARM9TDMI.
0.2% speedup on a 96 kbps enc+dec test on a Cortex A8.
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
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