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| author | Jean-Marc Valin <jean-marc.valin@usherbrooke.ca> | 2011-03-07 20:54:33 -0500 |
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| committer | Jean-Marc Valin <jean-marc.valin@usherbrooke.ca> | 2011-03-07 20:54:33 -0500 |
| commit | 0c0c5f940a3fc58c84b51765fc04f0294b42fd2d (patch) | |
| tree | c76599a271e0dd69db420da8cd5f55506d6d3773 /silk | |
| parent | f2b86588cd6db584968a2bace3007734e4fe6d1d (diff) | |
| download | opus-0c0c5f940a3fc58c84b51765fc04f0294b42fd2d.tar.gz | |
Support for glitchles mode switching
Uses a 5ms redundant CELT frame embedded into the SILK or hybrid
packet to handle the switching. It's still possible to use the
PLC-based method when no redundant packet is included.
Diffstat (limited to 'silk')
| m--------- | silk | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/silk b/silk -Subproject 37f9809a68b6c5ba514b0642e99231a7f68ee86 +Subproject 20832a6c95a84e18da936228e4b15823d8b8972 |