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| author | Jean-Marc Valin <jean-marc.valin@usherbrooke.ca> | 2011-03-07 20:54:33 -0500 |
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| committer | Jean-Marc Valin <jean-marc.valin@usherbrooke.ca> | 2011-03-07 20:54:33 -0500 |
| commit | 0c0c5f940a3fc58c84b51765fc04f0294b42fd2d (patch) | |
| tree | c76599a271e0dd69db420da8cd5f55506d6d3773 /celt/rate.c | |
| parent | f2b86588cd6db584968a2bace3007734e4fe6d1d (diff) | |
| download | opus-0c0c5f940a3fc58c84b51765fc04f0294b42fd2d.tar.gz | |
Support for glitchles mode switching
Uses a 5ms redundant CELT frame embedded into the SILK or hybrid
packet to handle the switching. It's still possible to use the
PLC-based method when no redundant packet is included.
Diffstat (limited to 'celt/rate.c')
| m--------- | celt | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/celt b/celt -Subproject c79c4e3bc7270b08a2800a2dd9d9a5f02767024 +Subproject 9bac8c17d57ea99192de09f8b97300b3dee0422 |