| Commit message (Collapse) | Author | Age | Files | Lines |
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'staging/secure_boot' into staging/work
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Add secure boot support for the GM20B chip found in Tegra X1. Secure
boot on Tegra works slightly differently from desktop, notably in the
way the WPR region is set up.
In addition, the firmware bootloaders use a slightly different header
format. This last point may be fixed when the actual firmware release
occurs, but for now this code makes it possible to load the firmware
released with SHIELD TV and Google Pixel C.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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This patch adds secure-boot for the dGPU set of GM20X chips, using the
PMU as the high-secure falcon.
This work is based on Deepak Goyal's initial port of Secure Boot to
Nouveau.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Trigger the loading of FECS/GPCCS using secure boot if required, and
start managed falcons using the CPUCTL_ALIAS register since CPUCTL is
protected in that case.
This solution (doing secure boot in GR) is temporary. In the future the
PMU firmware will be able to reboot falcons on demand, but this requires
the PMU firmware to be released first. This solution at least allows GR
to be enabled.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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On GM20x and later GPUs, firmware for some essential falcons (notably
FECS) must be authenticated by a NVIDIA-produced signature and loaded
by a high-secure falcon in order to access certain registers, in a
process known as Secure Boot.
Secure Boot requires the building of a binary blob containing the
firmwares and signatures of the falcons to be loaded. This blob is then
given to a high-secure falcon running a signed loader firmware that
copies the blob into a write-protected region, checks that the
signatures are valid, and finally loads the verified firmware into the
managed falcons and switches them to a priviledged mode.
This patch adds infrastructure code to support this process on chips
that require it.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Add memcpy functions that allow copying a buffer to a gpuobj and
vice-versa.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Use the newly-introduced nvkm_firmware functions. Note that this will
change the expected location of firmware files.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Use the newly-introduced nvkm_firmware functions. Note that this will
change the expected location of firmware files.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Use the newly-introduced nvkm_firmware functions. Note that this will
change the expected location of firmware files.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Use the nvkm_firmware_* functions when loading external firmware to
avoid duplicate code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Add two functions nvkm_firmware_get() and nvkm_firmware_put() to load a
firmware file and free its resources, respectively. Since firmware files
are becoming a necessity for new GPUs, and their location has been
standardized to nvidia/chip/, this will prevent duplicate and
error-prone name-generation code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Add a new NOUVEAU_GEM_PUSHBUF_2 ioctl that accepts and emits a sync
fence fd from/to user space if the user space requests it by passing
corresponding flags.
The new ioctl is only supported on relatively new chips, and it does
not support relocations or suffix0/suffix1.
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
[acourbot@nvidia.com: carry upstream, fix style]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Split this function to provide a version allowing to directly specify a
PB entry in its hardware format.
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
[acourbot@nvidia.com: split from longer patch]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Add nouveau_fence_install, which installs a drm fence as a file
descriptor that can be returned to user space.
Add nouveau_fence_sync_fd, which pushes semaphore wait commands for
each Nouveau fence contained within the sync fd. If the sync fd
contains non-Nouveau fences, those are waited on the CPU.
Add missing fence_value_str and timeline_value_str callbacks to
nouveau fence_ops.
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
[acourbot@nvidia.com: carry patch upstream]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Split nouveau_fence_sync to two functions:
* nouveau_fence_sync, which only adds a fence wait to the channel
command stream, and
* nouveau_bo_sync, which gets the fences from the reservation object
and passes them to nouveau_fence_sync.
This factorizes the code in the new nouveau_fence_sync() which was
present twice otherwise.
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
[acourbot@nvidia.com: factorize code some more, fix style]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Add new NOUVEAU_GEM_SET_TILING ioctl to set correct tiling
mode for imported dma-bufs. This ioctl is staging for now
and enabled with the "staging_tiling" module option.
Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com>
[acourbot@nvidia.com: carry upstream, many fixes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Need to factorize all the code in common with GK20A
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The CVB calculation and voltage setting functions can be reused for the
future chips. So move the declaration to gk20a.h.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
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We need the exact voltage value to calculate the PLL coefficients for
GM20B.
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
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The status bit used in gf100_gr_wait_idle only exists starting gk104.
As the function is currently used in gk20a and later, rename the function
to use gk104 prefix to reflex correct supported chip version.
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
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Fix the channel id bit mask in FIFO schedule timeout error handling.
FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff.
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
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See https://chromium-review.googlesource.com/#/c/305610/3
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When using the DMA-API for instmem, we may obtain a write-combined
mapping. For such cases, add a write barrier in
gk20a_instobj_release_dma() to make sure that all writes have reached
memory at this time.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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GM20B requires a channel kick to be performed during gpfifo cleanup, or
the FIFO will attempt to fetch memory from the previous context as a
channel is recycled. A previous commit attempted to do this for all
Kepler GPUs, but due to bug reports that pinned it down it has been
reverted. The present commit limits its scope to GM20B only.
The only effective change of this patch is to add a call to
gk104_fifo_gpfifo_kick() in gpfifo_fini for GM20B, but doing so requires
to export quite a few extra functions, hence its non-trivial length.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.
While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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v2: remove error and only set link for pcie devices
v6: remove check for pcie device
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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v2: rename functions
v3: remove pcie2 accessors
v6: fix alignement and line width, also remove useless code
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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v5: don't set kepler func pointers
v6: fix alignment and line length
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v5: don't set fermi or kepler func pointers
v6: fix alignment
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v2: rename and group functions
v4: change copyright information
move printing of pcie speeds into oneinit,
rename all pcie functions to nvkm_pcie_*
don't try to raise the pcie version when no higher one is supported
v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version
v6: remove some useless pci_is_pcie checks and rework messages
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
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fdo#93634
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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