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* Revert "ltc/gf100-: fix cbc issues on certain boards"baserock/jetson/gk20aAlexandre Courbot2014-11-045-7/+1
| | | | | | This reverts commit b15a810e97b8279cdbbfc90ede9e3fb51157f92b. Causes IOMMU errors on GK20A.
* HACK: drm/nouveau: prime: Pin buffer objects to VRAMThierry Reding2014-11-041-2/+31
| | | | | | | | | This is currently required to work around the lack of proper SMMU support on Tegra. Ideally buffer objects could always be pinned to GART and the SMMU will take care of mapping them to a linear I/O virtual address range for importers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* [HACK] add gk20a instmemAlexandre Courbot2014-11-048-9/+192
| | | | | This is a gazillion times faster, but requires to invalidate the GPU L2 (probably at a better place than this!)
* platform: support for netlist firmwaresAlexandre Courbot2014-11-043-5/+74
| | | | | | | | | | | | Netlists released by NVIDIA are made of a single file containing firmwares that can potentially be used across different engines. It therefore makes most sense to load a netlist once before engines are probed and have them duplicate their firmwares so the netlist can be freed at the end of probe. This patch implements this mechanism and adds the lookup data for GK20A. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* graph/nvc0: add support for netlist firmwaresAlexandre Courbot2014-11-043-0/+173
| | | | | | | | | | | NVIDIA is releasing some GPU firmwares for the Tegra SoCs under linux-firmware. The release format is a single file (called a netlist) containing all the firmwares relevant to a GPU, which must thus be extracted. This patch adds support for parsing the netlist and loading the firmwares for the NVC0 family of GPUs, falling back to the previous firmware lookup method is no netlist was already loaded. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* Experiments with large pagesAlexandre Courbot2014-11-044-9/+33
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* Revert "drm/nouveau/vm: fix mapping of SG pages list"Alexandre Courbot2014-11-041-7/+2
| | | | This reverts commit c7216ec42b8d17dd40a99ccf4d1060baf4bb28a1.
* drm/nouveau/vm: fix mapping of SG pages listAlexandre Courbot2014-11-041-2/+7
| | | | | | | | | | | | | | SG pages lists (not to be confused with scatterlists) are a list of 4KB memory pages used to define a nouveau_mem. Mapping them to a VM that does not use 4KB apertures resulted in each subsequent 4KB physical page being mapped into a larger VM aperture, thus creating an incorrect, overlapping mapping. This patch fixes this issue by detecting when such mappings occur and by skipping the required number of pages in the list to ensure a correct linear mapping. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: synchronize BOs when requiredAlexandre Courbot2014-10-313-0/+56
| | | | | | | | | | | | | | On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: allocate GPFIFOs and fences coherentlyAlexandre Courbot2014-10-312-3/+3
| | | | | | | | Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: implement explicitly coherent BOsAlexandre Courbot2014-10-312-8/+73
| | | | | | | | | | | | | | Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: introduce nv_device_is_cpu_coherent()Alexandre Courbot2014-10-312-0/+8
| | | | | | | | | | | Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: warn when moving a pinned objectAlexandre Courbot2014-10-311-2/+9
| | | | | | | | Pinned BOs are supposed to remain in their current location until unpinned. Display a warning for the supposedly-erroneous case where we are trying to move such objects. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm: fix regression on agp boardsBen Skeggs2014-10-311-6/+1
| | | | | | | | | Extends the fix in f2f9a2cbaf019481feefe231f996d3602612fa99 to also workaround permission issues noticed by people using AGP systems. Cc: stable@vger.kernel.org # 3.16: f2f9a2c: drm/nouveau: fix regression Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* v3.18-rc2Ben Skeggs2014-10-291-3/+9
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* gr/gt215: fix initialisation on gddr5 boardsBen Skeggs2014-10-201-2/+8
| | | | | | | | | | | The binary driver modifies the default context to have this value, rather than 0x3d0040, *after* it's filled the buffer with the usual golden data. We don't really have anything in place to locate the correct offset to do these type of modifications outside of the generation function, so this will have to do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* v3.18-rc1Ben Skeggs2014-10-202-4/+4
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* drm-next 7a42e83d36d2d0a68622320900dc4e880b1d920aBen Skeggs2014-10-0219-42/+91
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* drm-next 1dadba87cba20989c5a5a56f2a86fe6672e37c30Ben Skeggs2014-10-023-3/+4
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* disp/gt214-/dp: enable audioBen Skeggs2014-10-025-22/+30
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/gt214-: fix hda eld regressionBen Skeggs2014-10-021-8/+10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/g94-: calculate some dp audio constantsBen Skeggs2014-10-022-22/+49
| | | | | | | NVIDIA appear to have tweaked the algorithm from GF110, this implements the previous algorithm for them still. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/gt214-: perform hda codec setup on displayport tooBen Skeggs2014-10-021-2/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/gk104-: infoframe registers moved yet again on keplerBen Skeggs2014-10-028-3/+93
| | | | | | | Thanks to Vincent Pelletier for pointing this out and providing a proof of concept patch on the list. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: parse older ramcfg/timing data like we do newer onesBen Skeggs2014-10-027-132/+184
| | | | | | Done after discussion with Roy. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/nva3: Per-partition regsRoy Spliet2014-10-021-4/+4
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram: Support strided regsRoy Spliet2014-10-022-9/+38
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/nv50: Store the number of partitions in the designated fieldsRoy Spliet2014-10-022-10/+9
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/nv50: Set VBLANK time in modeset scriptRoy Spliet2014-10-021-3/+8
| | | | | | | | Solves blinking on reclocking memory. The value set is an underestimate, but with non-reduced vblanking this should give us plenty of time Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: Add rammap support for version 1.0Roy Spliet2014-10-021-0/+4
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/memx/gf100-: block host and fifo around reclockBen Skeggs2014-10-024-474/+632
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/memx: fix command ordering around block/unblockBen Skeggs2014-10-027-462/+461
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/memx: rename fb off/on to block/unblockBen Skeggs2014-10-026-22/+22
| | | | | | | | More accurate as to the function of the opcodes. Not only is FB disabled, but the host is prevented from touching the GPU. An upcoming patch for Kepler will also halt PFIFO (as NVIDIA does). Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: Pause the GPU before reclockingRoy Spliet2014-10-023-26/+66
| | | | | | | V2: always call post correctly even if pre fails V3: move function prototype to nva3.h Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
* gpio: rename g92 class to g94Emil Velikov2014-10-0210-32/+32
| | | | | | | | | | | | | | | | | nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104-: move fb enable/disable to same place as nvidiaBen Skeggs2014-10-021-5/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104: twiddle some more bits when reclockingBen Skeggs2014-10-021-1/+98
| | | | | | | *when* this is done is only a rough approximation of what the binary driver does.. need to investigate more to see if it matters Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: parse another large chunk of random memory config dataBen Skeggs2014-10-022-1/+24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104-: perform certain steps only when bios data differsBen Skeggs2014-10-022-21/+37
| | | | | | | Awful, awful. But, on the GK106 I have, some upcoming patches show that this is actually necessary after all. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104-: parse ramcfg data for all frequencies up-frontBen Skeggs2014-10-022-48/+89
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104-: use parsed timing data in mr routinesBen Skeggs2014-10-022-6/+11
| | | | | | | | All the other chipsets should be moved over to this too. It's not needed yet for the upcoming commits, so left this step as it'll conflict badly with Roy's GT21x reclocking work. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: parse freq ranges and timing id into ramcfg structBen Skeggs2014-10-027-26/+47
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: memset dcb struct to zero before parsingBen Skeggs2014-10-021-0/+1
| | | | | | | Fixes type/mask calculation being based on uninitialised data for VGA outputs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104: make use of training data provided by vbiosBen Skeggs2014-10-021-43/+138
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for parsing table at BIT 'M' v2 + 0x09Ben Skeggs2014-10-026-0/+171
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for parsing table at BIT 'M' v2 + 0x05Ben Skeggs2014-10-026-3/+175
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104: fix register for second set of training dataBen Skeggs2014-10-021-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104: more random magic in fb initBen Skeggs2014-10-021-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ram/gk104: skip table entry for mode we're already inBen Skeggs2014-10-021-11/+12
| | | | | | | NVIDIA binary driver appears to, not sure if it's for a good reason, but grasping at straws for some GDDR5 reclocking issues here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/sddr2: Generate MR valuesRoy Spliet2014-10-025-0/+100
| | | | | | | V2: Always disable DLL reset Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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