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author | Alexandre Courbot <acourbot@nvidia.com> | 2016-01-15 11:53:24 +0900 |
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committer | Ben Skeggs <bskeggs@redhat.com> | 2016-01-15 13:06:43 +1000 |
commit | eb87d86fd2c1395485d5cea93fe6159146fd1d9b (patch) | |
tree | baff498f73ba8639aa50918c02d7793432fc06bd /drm/nouveau/nouveau_bo.h | |
parent | b2274a3a71513836ad31405ef954cda3438c61d7 (diff) | |
download | nouveau-eb87d86fd2c1395485d5cea93fe6159146fd1d9b.tar.gz |
ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait
Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register is set. This happened at least
on GM206 when running glmark2-drm.
While we are at it, use the more compact nvkm_wait_msec() to wait for
the bit to clear.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drm/nouveau/nouveau_bo.h')
0 files changed, 0 insertions, 0 deletions