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authorXia Yang <xiay@nvidia.com>2015-12-07 16:37:08 -0800
committerAlexandre Courbot <acourbot@nvidia.com>2016-01-15 14:32:53 +0900
commit35d84b3b3cc604ec4ba1ab1f81a1f050ea2f5c20 (patch)
treec1716e02add13f0c57515bddbb87ffeaf9b66c75
parent038fae29d683b5b3f5f539d793c8dc4e85325dd3 (diff)
downloadnouveau-35d84b3b3cc604ec4ba1ab1f81a1f050ea2f5c20.tar.gz
gr: rename gf100_gr_wait_idle for gk104_*
The status bit used in gf100_gr_wait_idle only exists starting gk104. As the function is currently used in gk20a and later, rename the function to use gk104 prefix to reflex correct supported chip version. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
-rw-r--r--drm/nouveau/nvkm/engine/gr/ctxgk20a.c8
-rw-r--r--drm/nouveau/nvkm/engine/gr/ctxgm20b.c8
-rw-r--r--drm/nouveau/nvkm/engine/gr/gf100.c36
-rw-r--r--drm/nouveau/nvkm/engine/gr/gf100.h3
-rw-r--r--drm/nouveau/nvkm/engine/gr/gk104.c34
-rw-r--r--drm/nouveau/nvkm/engine/gr/gk20a.c2
6 files changed, 46 insertions, 45 deletions
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
index ad0a6cfe7..27be14cfa 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
+++ b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
@@ -34,7 +34,7 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
idle_timeout_save = nvkm_rd32(device, 0x404154);
nvkm_wr32(device, 0x404154, 0x00000000);
@@ -57,13 +57,13 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
nvkm_wr32(device, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->fuc_method);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->fuc_bundle);
grctx->pagepool(info);
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
index 670260402..c6062cadf 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
+++ b/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
@@ -45,7 +45,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, gr->fuc_sw_ctx);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
idle_timeout_save = nvkm_rd32(device, 0x404154);
nvkm_wr32(device, 0x404154, 0x00000000);
@@ -72,13 +72,13 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gm204_grctx_generate_405b60(gr);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
nvkm_wr32(device, 0x404154, idle_timeout_save);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->fuc_method);
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->fuc_bundle);
grctx->pagepool(info);
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c
index 1f81069ed..26ede00f8 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -729,40 +729,6 @@ gf100_gr_zbc_init(struct gf100_gr *gr)
gf100_gr_zbc_clear_depth(gr, index);
}
-/**
- * Wait until GR goes idle. GR is considered idle if it is disabled by the
- * MC (0x200) register, or GR is not busy and a context switch is not in
- * progress.
- */
-int
-gf100_gr_wait_idle(struct gf100_gr *gr)
-{
- struct nvkm_subdev *subdev = &gr->base.engine.subdev;
- struct nvkm_device *device = subdev->device;
- unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
- bool gr_enabled, ctxsw_active, gr_busy;
-
- do {
- /*
- * required to make sure FIFO_ENGINE_STATUS (0x2640) is
- * up-to-date
- */
- nvkm_rd32(device, 0x400700);
-
- gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
- ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
- gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
-
- if (!gr_enabled || (!gr_busy && !ctxsw_active))
- return 0;
- } while (time_before(jiffies, end_jiffies));
-
- nvkm_error(subdev,
- "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
- gr_enabled, ctxsw_active, gr_busy);
- return -EAGAIN;
-}
-
void
gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
@@ -806,7 +772,7 @@ gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
* GO_IDLE bundle
*/
if ((addr & 0xffff) == 0xe100)
- gf100_gr_wait_idle(gr);
+ gk104_gr_wait_idle(gr);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
break;
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.h b/drm/nouveau/nvkm/engine/gr/gf100.h
index 02e78b8d9..f42ac4650 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -198,12 +198,13 @@ extern struct gf100_gr_ucode gf100_gr_gpccs_ucode;
extern struct gf100_gr_ucode gk110_gr_fecs_ucode;
extern struct gf100_gr_ucode gk110_gr_gpccs_ucode;
-int gf100_gr_wait_idle(struct gf100_gr *);
void gf100_gr_mmio(struct gf100_gr *, const struct gf100_gr_pack *);
void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *);
void gf100_gr_mthd(struct gf100_gr *, const struct gf100_gr_pack *);
int gf100_gr_init_ctxctl(struct gf100_gr *);
+int gk104_gr_wait_idle(struct gf100_gr *);
+
/* register init value lists */
extern const struct gf100_gr_init gf100_gr_init_main_0[];
diff --git a/drm/nouveau/nvkm/engine/gr/gk104.c b/drm/nouveau/nvkm/engine/gr/gk104.c
index abf54928a..56f8d53e6 100644
--- a/drm/nouveau/nvkm/engine/gr/gk104.c
+++ b/drm/nouveau/nvkm/engine/gr/gk104.c
@@ -177,6 +177,40 @@ gk104_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
+/**
+ * Wait until GR goes idle. GR is considered idle if it is disabled by the
+ * MC (0x200) register, or GR is not busy and a context switch is not in
+ * progress.
+ */
+int
+gk104_gr_wait_idle(struct gf100_gr *gr)
+{
+ struct nvkm_subdev *subdev = &gr->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
+ unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
+ bool gr_enabled, ctxsw_active, gr_busy;
+
+ do {
+ /*
+ * required to make sure FIFO_ENGINE_STATUS (0x2640) is
+ * up-to-date
+ */
+ nvkm_rd32(device, 0x400700);
+
+ gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
+ ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
+ gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
+
+ if (!gr_enabled || (!gr_busy && !ctxsw_active))
+ return 0;
+ } while (time_before(jiffies, end_jiffies));
+
+ nvkm_error(subdev,
+ "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
+ gr_enabled, ctxsw_active, gr_busy);
+ return -EAGAIN;
+}
+
int
gk104_gr_init(struct gf100_gr *gr)
{
diff --git a/drm/nouveau/nvkm/engine/gr/gk20a.c b/drm/nouveau/nvkm/engine/gr/gk20a.c
index b8758d3b8..91a4d948e 100644
--- a/drm/nouveau/nvkm/engine/gr/gk20a.c
+++ b/drm/nouveau/nvkm/engine/gr/gk20a.c
@@ -198,7 +198,7 @@ gk20a_gr_init(struct gf100_gr *gr)
if (ret)
return ret;
- ret = gf100_gr_wait_idle(gr);
+ ret = gk104_gr_wait_idle(gr);
if (ret)
return ret;