diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2015-10-28 17:54:37 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-01-15 14:32:54 +0900 |
| commit | 29c4745813fb44fc5e65f723b6419e6f47630cf5 (patch) | |
| tree | d409a5a3ebfb23bda4920f53c2ffac15fc6c9aab | |
| parent | 61ac49119f3466d173040eb661c46bf63b73b1b6 (diff) | |
| download | nouveau-29c4745813fb44fc5e65f723b6419e6f47630cf5.tar.gz | |
optimize gm20b
| -rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gm20b.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 74211d166..d3a81dca6 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -862,8 +862,7 @@ _gm20b_pllg_program_na_mnp(struct gm20b_clk *clk, struct nvkm_volt *volt = device->volt; int cur_uv = nvkm_volt_get(volt); int new_uv = nvkm_volt_get_voltage_by_id(volt, clk->vid); - struct gm20b_gpcpll *last_gpcpll = &clk->last_gpcpll; - u32 cur_rate = last_gpcpll->rate; + u32 cur_rate = clk->last_gpcpll.rate; gm20b_clk_config_dvfs(clk); @@ -871,7 +870,7 @@ _gm20b_pllg_program_na_mnp(struct gm20b_clk *clk, * We don't have to re-program the DVFS because the voltage keeps the * same value (and we already have the same coeffients in hardware). */ - if (!allow_slide || last_gpcpll->dvfs.uv == gpcpll->dvfs.uv) + if (!allow_slide || clk->last_gpcpll.dvfs.uv == gpcpll->dvfs.uv) return _gm20b_pllg_program_mnp(clk, &clk->gpcpll, allow_slide); /* Before setting coefficient to 0, switch to safe frequency first */ |