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| author | Xia Yang <xiay@nvidia.com> | 2015-12-07 16:28:01 -0800 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-01-15 14:32:53 +0900 |
| commit | 038fae29d683b5b3f5f539d793c8dc4e85325dd3 (patch) | |
| tree | 19138f38814996465c6533270470730135d01a05 | |
| parent | 0c57c34d9b2bacc3da52a43b144aea3326df52b9 (diff) | |
| download | nouveau-038fae29d683b5b3f5f539d793c8dc4e85325dd3.tar.gz | |
fifo/gk104: fix chid bit mask
Fix the channel id bit mask in FIFO schedule timeout error handling.
FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff.
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
| -rw-r--r-- | drm/nouveau/nvkm/engine/fifo/gk104.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drm/nouveau/nvkm/engine/fifo/gk104.c b/drm/nouveau/nvkm/engine/fifo/gk104.c index 4fcd147d4..d6a88cf67 100644 --- a/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -198,11 +198,11 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); u32 busy = (stat & 0x80000000); - u32 next = (stat & 0x07ff0000) >> 16; + u32 next = (stat & 0x0fff0000) >> 16; u32 chsw = (stat & 0x00008000); u32 save = (stat & 0x00004000); u32 load = (stat & 0x00002000); - u32 prev = (stat & 0x000007ff); + u32 prev = (stat & 0x00000fff); u32 chid = load ? next : prev; (void)save; |