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PROLOGUE
One day someone wrote that nasm needs:
> - A good ALIGN mechanism, similar to GAS's. GAS pads out space by
> means of the following (32-bit) instructions:
> 8DB42600000000 lea esi,[esi+0x0]
> 8DB600000000 lea esi,[esi+0x0]
> 8D742600 lea esi,[esi+0x0]
> 8D7600 lea esi,[esi+0x0]
> 8D36 lea esi,[esi]
> 90 nop
> It uses up to two of these instructions to do up to 14-byte pads;
> when more than 14 bytes are needed, it issues a (short) jump to
> the end of the padded section and then NOPs the rest. Come up with
> a similar scheme for 16 bit mode, and also come up with a way to
> use it - internal to the assembler, so that programs using ALIGN
> don't knock over preprocess-only mode.
> Also re-work the macro form so that when given one argument in a
> code section it calls this feature.
Well palign is your friend.
This is a modified version of nasm-0.98.24 that can accept
two new directives.The two new directives that control
the align mechanism are 'palign' and 'p2align'.They are nasm directives
that don't depend on preprocessor but rather align the code while assembling
in a gas-like style.
The syntax of these directives is
[palign n] where '0 <= n <= 6' and
[p2align n] where '0 <= n <=6'
The use of these directives is
[palign n]
Pad the location counter to a particular storage boundary.
The n is a number between 0 and 6 of low-order zero bits the location counter
must have after advancement.
For example `palign 3' advances the location counter until
it a multiple of 8.If the location counter is already a multiple of 8,
no change is needed.
If n=0 then nothing is done
if n => 6 then palign advances the location counter until it a multiple
of 64.For now the maximum is 64 bytes,if you want more use the ALIGN macro.
[p2align n]
This directive do almost the same thing with a little exception.
It will continue aligning until a directive [p2align 0] meet or until
the current section changes.So this piece of code
BITS 32
SECTION .text
[p2align 5]
;some code here
SECTION .data
;some data here
guarantee that all the instructions in the code segment will be aligned
in a 32 byte boundary so than no instruction break the cache line on a
pentium processor.
BUGS
Well my english are very very bad.
This optimization will not work
for now for 16-bit code.
Also there may be a problem with the prefixes like ds,es,rep,lock etc
so this code will work
'rep movsd'
but this may not work
'rep'
'movsd'
if you want to be sure put the prefix in the same line
with the instruction.
Also don't try this in a data or a bss segment.Use the ALIGN macro better
FEEDBACK
If you have any suggestion, comment or found a bug please email me
and i will try to reply immediately.
From your feedback it depends this project to get better as i intend
to implement more things and improve the code in the next version of nasm.
AUTHOR
Panos Minos 03-04-2002
email: <panosminos@mycosmos.gr> , <panosminos1@mycosmos.gr>
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