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* ndisasm: handle VEX.LIGH. Peter Anvin2010-08-191-1/+1
| | | | | | | | A lot of instructions ignore the L bit in the VEX prefix, just like a lot of instructions ignore the W bit, so don't use them in the sub-table select. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* Enable fuzzy matching of operand sizesH. Peter Anvin2009-07-251-11/+14
| | | | | | | | | | | | | | This allows automatic fuzzy matching of operand sizes. If an operand size is not specified, but there is exactly one possible size for the instruction, select that instruction size. This requires a second pass through the instruction patterns, and so is slightly slower, but should be a lot easier to get right than the S- flags, and works even when there is more than one instruction. The new SX (Size eXact) flag can be used to prevent fuzzy matching completely. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Use lower case for VEX and XOP in instructions tableH. Peter Anvin2009-05-031-1/+1
| | | | | | | | Use lower case for VEX and XOP ("vex", "xop") to avoid visual confusion (and in the future potential real confusion) with upper-case hexadecimal numbers. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Infrastructure support for AMD's new XOP prefixH. Peter Anvin2009-05-031-1/+1
| | | | | | | Handle AMD's XOP prefixes; they use basically the same encoding as VEX prefixes, so treat them simply as a variant of VEX. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* FMA instructions won't be in Sandy BridgeH. Peter Anvin2009-02-211-0/+1
| | | | | The FMA instructions aren't scheduled for Sandy Bridge after all. They will be "in a future processor", so create a placeholder for now.
* AVX FMA: Instruction table for the AVX FMA instructionsH. Peter Anvin2008-05-231-1/+2
| | | | | This adds the AVX FMA instructions to the instruction table, which should complete the AVX work.
* Disassembler: select table based on VEX prefixesH. Peter Anvin2008-05-211-0/+1
| | | | | | | | | | We can use the new VEX prefixes to select into a large table of new opcode spaces. Since the table is (currently) sparse, add logic so we don't end up producing tons of empty tables for no good reason. This is also necessary since VEX is likely to reuse opcode bytes that would appear as prefixes at some point, which would cause conflicts with the regular tables.
* Add DY, YWORD, and the SY instruction flagH. Peter Anvin2008-05-201-1/+2
| | | | | Add the DY instruction, YWORD keyword, and an SY marker for instruction sizes. Add a few more AVX sample instructions.
* Make insnsb.c an actual compilation unitH. Peter Anvin2008-05-131-0/+3
| | | | | | | "make alldeps" doesn't really like it when included files end in *.c. Instead of renaming insnsb.c to insnsb.h, make it an actual compilation unit, since there really isn't any reason for it not to be.
* Generate a byte array instead of using strings for the byte codesH. Peter Anvin2008-05-121-1/+1
| | | | | | | | | | | Generate a byte array instead of using C compiler strings for the byte codes. This has a few advantages: - No need to special-case zero due to broken C compilers. - Only insns.pl only ever reads the string, so we can invent our own syntax. - Compaction. - We can give it the proper, unsigned type.
* Actually spell "Sandy Bridge" correctlyH. Peter Anvin2008-05-061-1/+1
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* Sandy Bridge, not Sandy Banks; add WestmereH. Peter Anvin2008-05-061-1/+2
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* First cut at AVX machinery.H. Peter Anvin2008-05-041-0/+2
| | | | | | | | | First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
* Correctly identify SBYTE in the optimizerH. Peter Anvin2008-04-041-1/+3
| | | | | Correctly identify SBYTE in the optimizer, *HOWEVER*, this change will cause nuisance warnings to be issued; that will have to be fixed.
* regularized spelling of license to match name of LICENSE fileBeroset2007-12-291-1/+1
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* Support __float*__ for floating-point numbers in expressionsH. Peter Anvin2007-09-241-7/+1
| | | | | | | | | Add special operators to allow the use of floating-point constants in contexts other than DW/DD/DQ/DT/DO. As part of this checkin, make MAX_KEYWORD generated by tokhash.pl, since it knows what all the keywords are so it can tell which one is the longest.
* Add the AMD SSE4a and LZCNT instructionsH. Peter Anvin2007-09-221-2/+3
| | | | Add AMD SSE4a and LZCNT
* Support generating NaNs and infinitiesH. Peter Anvin2007-09-181-2/+2
| | | | | Support generating NaNs and infinities as part of floating-point constants.
* Speed up the disassembler by allowing prefixed instruction tablesH. Peter Anvin2007-09-181-1/+10
| | | | | | | Modify the disassembler so that we can have separate instruction tables for prefixed instructions. As it was, all instructions which started with 0F were linearly searched, and that is by now more than half the instruction set.
* Implement "oword" (128 bits) as a first-class sizeH. Peter Anvin2007-09-181-0/+1
| | | | | | Implement oword, reso, do, as well as the SO flag to instructions. No instructions are actually flagged with SO yet, but this allows us to specify 128-bit sizes in instruction patterns.
* Actually generate SSE5 instructionsH. Peter Anvin2007-09-171-1/+2
| | | | | | | | | | This checkin completes what is required to actually generate SSE5 instructions. No support in the disassembler yet. This checkin covers: - Support for actually generating DREX prefixes. - Support for matching operand "operand X must match Y"
* Initial support for four arguments per instructionH. Peter Anvin2007-09-171-8/+10
| | | | For SSE5, we will need to support four arguments per instruction.
* Add (untested!) SSSE3, SSE4.1, SSE4.2 instructionsH. Peter Anvin2007-09-121-0/+1
| | | | | | | | | | Add the SSSE3, SSE4.1 and SSE4.2 instruction sets. Change \332 to be a literal 0xF2 prefix, by analog with \333 for 0xF3 prefix (the previous \332 flag changed to \335). This is necessary to get the REX prefix in the right place for instructions that use it. We are going to have to go in and change existing instruction patterns which use these, as well.
* Remove $Id$ tags (useless with git)H. Peter Anvin2007-09-121-1/+0
| | | | Remove CVS $Id$ tags, since git doesn't use them.
* Macros for SSSE3/SSE4 instruction setsH. Peter Anvin2007-09-121-0/+3
| | | | | Add instruction set flags for the SSSE3, SSE4.1 and SSE4.2 instruction subsets.
* Make the big instruction arrays "const"H. Peter Anvin2007-09-111-0/+4
| | | | | Make the big instruction arrays "const", so they end up in readonly storage. While we're at it, move their prototypes into insns.h.
* Use an actual enum for the opcodeH. Peter Anvin2007-09-101-5/+5
| | | | | Use an actual named enum for the opcode, that way it shows up in cleartext while debugging.
* Handle "LOCK as REX.R" for MOV CRx; fix warning for invalid 64-bit regsH. Peter Anvin2007-04-171-3/+5
| | | | | | | - MOV gpr,CRx or MOV CRx,gpr can access high control registers with a LOCK prefix; handle that in both the assembler and disassembler. - Get a saner error message when trying to access high resources in non-64-bit mode.
* Fixed distinction between char and int8_t data types.Keith Kanios2007-04-131-1/+1
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* General push for x86-64 support, dubbed 0.99.00.Keith Kanios2007-04-121-8/+11
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* Add VMX instructions.nasm-0.98.xEric Christopher2006-03-021-2/+3
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* Apply Nindent to all .c and .h filesnasm-0.98.39LATESTH. Peter Anvin2005-01-151-43/+43
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* Add support for the new instructions in PrescottH. Peter Anvin2003-02-241-0/+2
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* Clean up unnecessary dependencies.H. Peter Anvin2002-09-121-0/+9
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* Add the JMPE instruction.H. Peter Anvin2002-05-281-0/+1
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* Code cleanup fixes from Ed BerosetH. Peter Anvin2002-05-141-1/+6
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* NASM 0.98.08nasm-0.98.08H. Peter Anvin2002-04-301-0/+2
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* NASM 0.98.03nasm-0.98.03H. Peter Anvin2002-04-301-0/+2
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* NASM 0.98p7nasm-0.98p7H. Peter Anvin2002-04-301-0/+5
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* NASM 0.98p3.5nasm-0.98p3.5H. Peter Anvin2002-04-301-19/+26
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* NASM 0.96nasm-0.96H. Peter Anvin2002-04-301-0/+1
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* NASM 0.94nasm-0.94H. Peter Anvin2002-04-301-16/+15
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* NASM 0.91nasm-0.91H. Peter Anvin2002-04-301-0/+66
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