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* BR3189064: Fixes for VEXTRACTF128, VMASKMOVPSCyrill Gorcunov2011-03-071-2/+2
* insns: VLDQQU is backCyrill Gorcunov2011-02-231-0/+1
* BR 3187743: insns.dat -- Rename VLDQQU to VLDDQUCyrill Gorcunov2011-02-211-1/+1
* Delete invalid form of VPEXTRWCyrill Gorcunov2011-02-201-1/+0
* BR3174983: insns.dat -- Fix arguments encodong for VPEXTRWCyrill Gorcunov2011-02-141-2/+2
* insns.dat: permit contracted forms for VBLENDVPH. Peter Anvin2010-08-161-4/+4
* insns.dat: fix encoding of VCVTSD2SSH. Peter Anvin2010-08-161-1/+1
* insns.dat: SSE encoding of VBLEND with VEX prefix is forbiddenH. Peter Anvin2010-08-161-4/+0
* insns.dat: updates from AVX v7H. Peter Anvin2010-08-161-184/+235
* insns.dat: unbreak test/imm64.binH. Peter Anvin2010-08-021-1/+1
* insns: add FXSAVE64/FXRSTOR64, drop np prefixH. Peter Anvin2010-07-071-7/+9
* Merge branch 'master' of ssh://repo.or.cz/srv/git/nasmH. Peter Anvin2010-07-071-14/+26
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| * insns.dat: add XSAVE/XRSTOR64, XSAVEOPT, VCVTPH2PS/VCVTPS2PHH. Peter Anvin2010-07-071-14/+26
* | insns.dat: remove VCVTPH2PS/VCVTPS2PH as AMD instructionsH. Peter Anvin2010-07-061-10/+2
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* insns.dat: fix CPU flags for new instructionsH. Peter Anvin2010-07-061-9/+9
* Add RD*SBASE, WR*SBASE, RDRAND from AVX v7H. Peter Anvin2010-07-061-0/+11
* BR 3020760: insns.dat -- confirm push imm32 on x86-64 explicitlyCyrill Gorcunov2010-06-251-0/+1
* BR 3018233: handle LFS, LGS and LSS with a 64-bit registerH. Peter Anvin2010-06-181-1/+4
* BR2975768: Update AMD LWP instructions to match upcoming changesCyrill Gorcunov2010-03-251-8/+9
* insns.dat: in 64-bit mode, accept "monitor rax,ecx,edx".H. Peter Anvin2010-01-061-0/+1
* BR2924380: Add AMD LWP instructionsCyrill Gorcunov2010-01-031-0/+20
* BR2924383: fix XOP instructionsCyrill Gorcunov2010-01-031-4/+10
* BR2924583: fix FMA4 instructionsCyrill Gorcunov2010-01-031-2/+2
* insns.dat: Restore default size of memory operandsCyrill Gorcunov2009-12-161-22/+22
* insns.dat: AVX -- no need for IF_ARx in templateCyrill Gorcunov2009-12-031-12/+12
* insns.dat: remove non-DREX SSE5 instructionsH. Peter Anvin2009-11-091-31/+0
* SSE5: remove all DREX-based instructionsH. Peter Anvin2009-11-091-275/+1
* MOVD xmmreg: not valid with REX.WH. Peter Anvin2009-11-061-4/+4
* IMUL: sbyteX fix -- last oneCyrill Gorcunov2009-11-031-3/+3
* IMUL: fix an additional incorrect sbyte useH. Peter Anvin2009-11-031-1/+1
* BR 2887108: fix incorrect sbyte usage in IMULH. Peter Anvin2009-11-031-2/+2
* insns.dat -- convert FMA instructionsCyrill Gorcunov2009-08-071-192/+192
* insns.dat -- convert AVX instructions part2Cyrill Gorcunov2009-08-071-347/+347
* insns.dat -- convert AVX instructions part1Cyrill Gorcunov2009-08-071-281/+281
* insns.dat: operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-18/+18
* insns.dat -- operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-150/+150
* Add copyright notice to insns.datH. Peter Anvin2009-06-281-6/+35
* ndisasm: fix disassembly of JRCXZH. Peter Anvin2009-06-261-1/+1
* insns.dat: reformatH. Peter Anvin2009-06-261-104/+104
* insns.dat: add relaxed forms for XOP/FMA4/CVT16 instructionsH. Peter Anvin2009-06-261-146/+148
* insns: make the MMX version of PINSRW match the SSE/AVX onesH. Peter Anvin2009-06-241-3/+3
* Intel FMA: drop relaxed formsH. Peter Anvin2009-06-241-192/+192
* Fix the PINSR series of instructionsH. Peter Anvin2009-06-241-18/+21
* insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin2009-06-241-4/+2
* insns.dat: collapse relaxed formsH. Peter Anvin2009-06-241-1212/+608
* insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-171-13/+23
* insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-151-0/+199
* BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin2009-03-171-264/+264
* BR 2690688: add missing VFM instructionsH. Peter Anvin2009-03-171-24/+168
* BR 2689316: PEXTRQ requires REX.WH. Peter Anvin2009-03-161-1/+1
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