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* insns.dat: permit contracted forms for VBLENDVPH. Peter Anvin2010-08-161-4/+4
| | | | | | | Allow implicit operands for VBLENDVP, just as for other instructions, since the semi-legacy forms now are removed. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* insns.dat: fix encoding of VCVTSD2SSH. Peter Anvin2010-08-161-1/+1
| | | | | | Fix typo in the definition of VCVTSD2SS. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* insns.dat: SSE encoding of VBLEND with VEX prefix is forbiddenH. Peter Anvin2010-08-161-4/+0
| | | | | | | | Version 7 of the AVX spec specifically forbids (#UD) using the 66 0F 38 14/15 forms of the BLENDV instructions with a VEX prefix; those encodings are strictly legacy SSE 4.1. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* insns.dat: updates from AVX v7H. Peter Anvin2010-08-161-184/+235
| | | | | | | | | | Updates from the AVX version 7 specification: mostly tightening of the rules for VEX.L and VEX.W, but remove the VPERMIL2 instructions. Also encode all the full-length forms of the VCMP instructions and prefer those for the disassembly. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* insns.dat: unbreak test/imm64.binH. Peter Anvin2010-08-021-1/+1
| | | | | | | | Unbreak the following subtest in test/imm64.bin: mov qword [rax],dword 11223344h Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* insns: add FXSAVE64/FXRSTOR64, drop np prefixH. Peter Anvin2010-07-071-7/+9
| | | | | | | | Add FXSAVE64 and FXRSTOR64; drop the np prefix on 0F AE instructions: none of the rest of the 0F AE instructions have them, and there are no conflicts. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Merge branch 'master' of ssh://repo.or.cz/srv/git/nasmH. Peter Anvin2010-07-071-14/+26
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| * insns.dat: add XSAVE/XRSTOR64, XSAVEOPT, VCVTPH2PS/VCVTPS2PHH. Peter Anvin2010-07-071-14/+26
| | | | | | | | | | | | | | Add XSAVE64/XRSTOR64 (previously missing), XSAVEOPT/XSAVEOPT64 (per AVX 007 spec), and VCVTPH2PS/VCVTPS2PH (per AVX 007) spec. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* | insns.dat: remove VCVTPH2PS/VCVTPS2PH as AMD instructionsH. Peter Anvin2010-07-061-10/+2
|/ | | | | | | Remove VCVTPH2PS/VCVTPS2PH as AMD instructions based on version 3.04 of the AMD spec. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: fix CPU flags for new instructionsH. Peter Anvin2010-07-061-9/+9
| | | | | | | | FUTURE is a CPU level flag, and cannot be combined with X64 (which is shorthand for X86_64,LONG). Also, make sure we add LONG annotations to everything that is 64-bit mode only. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Add RD*SBASE, WR*SBASE, RDRAND from AVX v7H. Peter Anvin2010-07-061-0/+11
| | | | | | | Add the RD*SBASE, WR*SBASE and RDRAND instructions from version 7 of the AVX specification, Intel document 319433-007. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* BR 3020760: insns.dat -- confirm push imm32 on x86-64 explicitlyCyrill Gorcunov2010-06-251-0/+1
| | | | | | | | | | | | | | | | PUSH imm64 confuses ones who is trying to find this instruction in processor programming manuals. Actually it was introduced in a sake of "push `size' imm" consistency. In other words -- to allow users to state "PUSH qword imm32" in 64bit code, though on byte level (ie generated) code it still has a correct and valid sign-extended "PUSH imm32" instruction. To get rid of this ambiguie bite we make explicit "PUSH imm32" being valid in 64bit code. This also makes "PUSH dword imm32" valid in 64bit code as well. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* BR 3018233: handle LFS, LGS and LSS with a 64-bit registerH. Peter Anvin2010-06-181-1/+4
| | | | | | | LFS, LGS and LSS are valid in 64-bit mode and have 64-bit (REX.W) forms. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* BR2975768: Update AMD LWP instructions to match upcoming changesCyrill Gorcunov2010-03-251-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The former changes have been committed to binutils. From initial message: | | 2010-03-22 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop <sebastian.pop@amd.com> | | opcodes/ | * i386-dis.c (OP_LWP_I): Removed. | (reg_table): Do not use OP_LWP_I, use Iq. | (OP_LWPCB_E): Remove use of names16. | (OP_LWP_E): Same. | * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns | should not set the Vex.length bit. | * i386-tbl.h: Regenerated. | | gas/ | * testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns. | * testsuite/gas/i386/lwp.s: Same. | * testsuite/gas/i386/x86-64-lwp.d: Updated. | * testsuite/gas/i386/lwp.d: Updated. | So there is no 16 bit instructions anymore. Also xop.l field should be set to 0. Based on patch from nasm64developer Reported-by: nasm64developer Signed-off-by: nasm64developer Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: in 64-bit mode, accept "monitor rax,ecx,edx".H. Peter Anvin2010-01-061-0/+1
| | | | | | | | | The first argument to MONITOR is an address, so it should be 64 bits (RAX) in 64-bit mode. The preferred form is still just plain "monitor". Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* BR2924380: Add AMD LWP instructionsCyrill Gorcunov2010-01-031-0/+20
| | | | | | | | nasm64developer reported that we have no LWP support yet. Add this feature. Reported-by: nasm64developer <nasm64developer@users.sf.net> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* BR2924383: fix XOP instructionsCyrill Gorcunov2010-01-031-4/+10
| | | | | | | | | | nasm64developer reported a few nits in XOP instruction templates. Plain typo in specification (http://support.amd.com/us/Processor_TechDocs/43479.pdf) and opcode errors. Reported-by: nasm64developer <nasm64developer@users.sf.net> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* BR2924583: fix FMA4 instructionsCyrill Gorcunov2010-01-031-2/+2
| | | | | | | | | nasm64developer reported that VFNMADDSD and VFNMADDSS have "m" and "s" operands swapped in instruction templates file. Reported-by: nasm64developer <nasm64developer@users.sf.net> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: Restore default size of memory operandsCyrill Gorcunov2009-12-161-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | During conversion of size of memory operands into explicit form the compatibility with 2.07 has been broken (for a small set of instructions). Lets restore it. Details below. This is due to specifics of our "fuzzy logic" algorithm. For example consider the user wrote an instruction like VCVTTPD2DQ xmm0,[eax] the last operand is memory reference. But template contains the following two items (written in simplified form) VCVTTPD2DQ xmmreg,mem128 VCVTTPD2DQ xmmreg,mem256 So this is impossible to find out what _exactly_ user meant: either reference to 128 bit value in memory or 256 bit. As a solution we've been using IF_Sx modifier written in template which allows to choose "by-default" template and break the tie. Reported-by: Victor van den Elzen <victor.vde@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: AVX -- no need for IF_ARx in templateCyrill Gorcunov2009-12-031-12/+12
| | | | | | | We describe the instruction arguments in explicit form so IF_ARx is just not needed here. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: remove non-DREX SSE5 instructionsH. Peter Anvin2009-11-091-31/+0
| | | | | | | | | Even the non-DREX SSE5 instructions appear to have been either obsoleted or replaced with XOP varieties. The only exception are the ROUNDxx instructions, which are really SSE4.1 instructions and which were simply duplicates. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* SSE5: remove all DREX-based instructionsH. Peter Anvin2009-11-091-275/+1
| | | | | | | AMD has obsoleted the DREX-based SSE5 proposal, so remove all such instructions. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* MOVD xmmreg: not valid with REX.WH. Peter Anvin2009-11-061-4/+4
| | | | | | | The xmmreg forms of MOVD are invalid with REX.W, since those are MOVQ instructions. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* IMUL: sbyteX fix -- last oneCyrill Gorcunov2009-11-031-3/+3
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* IMUL: fix an additional incorrect sbyte useH. Peter Anvin2009-11-031-1/+1
| | | | | | | | | | | One more incorrect use of sbyte in IMUL. Overall, the IMUL patterns seem really messy. *Furthermore*, despite IMUL normally being thought of as signed, the 2- and 3-operand versions don't produce a high half and are therefore signedness-agnostic -- we could even add MUL patterns for those forms. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* BR 2887108: fix incorrect sbyte usage in IMULH. Peter Anvin2009-11-031-2/+2
| | | | | | | | Fix a very curious transposition in the instruction patterns for IMUL, which caused 32-bit IMUL instructions with constants like 0x10001 to be generated incorrectly. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat -- convert FMA instructionsCyrill Gorcunov2009-08-071-192/+192
| | | | | | Convert FMA instructions to explicit sized ones. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat -- convert AVX instructions part2Cyrill Gorcunov2009-08-071-347/+347
| | | | | | | | | | | | | Convert Intel AVX instructions to explisit size format. Part 2. Also CLMUL converted as well. Btw, VPINSR was a bit broken since SB constraint is not applied on all forms but requires 16,32,64 memory sizes too. Fixed. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat -- convert AVX instructions part1Cyrill Gorcunov2009-08-071-281/+281
| | | | | | | | | Convert Intel AVX instructions to explisit size format. Part 1. Also SAR instruction is touched as well. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-18/+18
| | | | | | Explicitly declare the sizes of immediate fields. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat -- operand-size syntax for XOP instructionsCyrill Gorcunov2009-07-271-150/+150
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Add copyright notice to insns.datH. Peter Anvin2009-06-281-6/+35
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* ndisasm: fix disassembly of JRCXZH. Peter Anvin2009-06-261-1/+1
| | | | | | | Fix the disassembly of JRCXZ; in 64-bit mode, we should only accept JECXZ for disassembly with 32-bit address size override. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: reformatH. Peter Anvin2009-06-261-104/+104
| | | | | | Reformat insns.dat with standard formatting Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: add relaxed forms for XOP/FMA4/CVT16 instructionsH. Peter Anvin2009-06-261-146/+148
| | | | | | | Add relaxed forms of the XOP/FMA4/CVT16 instructions, without looking too hard at if it makes sense. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns: make the MMX version of PINSRW match the SSE/AVX onesH. Peter Anvin2009-06-241-3/+3
| | | | | | | Make the MMX version of PINSRW match the SSE and AVX ones, and add it to the tests. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Intel FMA: drop relaxed formsH. Peter Anvin2009-06-241-192/+192
| | | | | | | The Intel FMA instructions are destructive, so relaxed forms are not appropriate. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Fix the PINSR series of instructionsH. Peter Anvin2009-06-241-18/+21
| | | | | | Clean up a number of errors in the PINSR series instructions. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: fix typos: VCMPORD_SP[SD] entered as VCMPORS_SP[SD]H. Peter Anvin2009-06-241-4/+2
| | | | | | Fix typos in two instructions in the relaxed forms. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: collapse relaxed formsH. Peter Anvin2009-06-241-1212/+608
| | | | | | | | | | | | | Change the relaxed forms to the compact representation. This *deliberately* does not fix bugs where the relaxed form does not match the official form; this is strictly a "no change in output" checkin. All remaining open-coded relaxed forms are very likely bugs, and need to be individually audited. Furthermore, it is questionable if the Intel FMA instructions, being destructive, should have relaxed forms at all. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat - fixup for XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-171-13/+23
| | | | | | | | | | 1) A number of PMA -> VPM misprint fixed. 2) Spec points to ymmreg in mnemonics even for L=0 instructions. Fixed. The instructions are still sorted in order of specification follows. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat - introcuce base XOP (SSE5) AMD instructionsCyrill Gorcunov2009-05-151-0/+199
| | | | | | | | | | Introduce base XOP/FMA4/CVT16 instructions (SSE5) based on official specification from AMD (rev 3.03). Some fixes from Peter Johnson and H. Peter Anvin included (not updated in AMD spec yet). Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* BR 2690688: Fix opcodes for FMA instructionsH. Peter Anvin2009-03-171-264/+264
| | | | | | Two bugs with respect to the FMA instructions: - the variant increment is supposed to be 0x10, not 0x01. - the base opcode for scalar VFNMADD is 0x9d, not 0x9c
* BR 2690688: add missing VFM instructionsH. Peter Anvin2009-03-171-24/+168
| | | | | | The Perl script which auto-generated the VFM instructions had incorrectly conflated the VEX.W and VEX.L bits, with the result that only half the valid instructions were generated.
* BR 2689316: PEXTRQ requires REX.WH. Peter Anvin2009-03-161-1/+1
| | | | The PEXTRQ instruction requires a REX.W prefix.
* insns.dat: fix VFNM instructions incorrectly spelled as VFMNH. Peter Anvin2009-03-161-48/+48
| | | | | The scalar versions of the VFNM instructions had been incorrectly spelled VFMN.
* Add VPCLMUL instructionsH. Peter Anvin2009-02-231-0/+12
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* PCLMUL is apparently targeted for Westmere with the AES stuffH. Peter Anvin2009-02-211-6/+5
| | | | The PCLMUL instruction is apparently targetted for Westmere.
* BR 2557903: fix disassembly of a set of SSE MOV* instructionsH. Peter Anvin2009-02-211-6/+6
| | | | | | | | Fix the disassembly of the alternate forms of register-register MOVAPD, MOVDQA, MOVDQU, MOVQ, MOVSD, and MOVUPD. NASM never generates these, but they would be disassembled incorrectly.
* BR 2541252: Fix issues in insns.dat, mostly related to LZCNT and POPCNTH. Peter Anvin2009-02-211-10/+10
| | | | | Fix various flags on LZCNT and POPCNT, and fix a few instructions tagged \360\332, which makes no sense.
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