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* BR3064376: ndisasm crashCyrill Gorcunov2010-09-151-1/+1
| | | | | | ndisasm may crash due to lack of check of VEX table index. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* ndisasm: handle VEX.LIGH. Peter Anvin2010-08-191-1/+1
| | | | | | | | A lot of instructions ignore the L bit in the VEX prefix, just like a lot of instructions ignore the W bit, so don't use them in the sub-table select. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* ndisasm: unify VEX handlingH. Peter Anvin2010-08-191-34/+6
| | | | | | Unify VEX handling between the 026x and 0270 bytecodes. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* ndisasm: fix handing of byte codes 250-253, 324H. Peter Anvin2010-08-161-2/+12
| | | | | | | Fix handling of byte codes 250-253 (sign-extended 32-bit immediate, extended to 64 bits) and 324 (instruction must have osize 64). Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* assemble: handle vex.ligH. Peter Anvin2010-08-161-5/+7
| | | | | | | AVX version 7 introduces the concept of .lig, meaning VEX.L is ignored. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* continue using is_class helperCyrill Gorcunov2009-10-181-2/+2
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* opflags: more int32_t -> opflags_t conversionsH. Peter Anvin2009-10-131-1/+1
| | | | | | | Hopefully this should catch all of them... but please keep an eye out for any other uses of int32_t for the operand flags. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* disasm.c: eatbyte -- use snprintf to prevent potential buffer overflowCyrill Gorcunov2009-08-091-1/+1
| | | | | | | | At moment we can't overrun buffer even if we would like to but better to stay on a safe side and use snprintf. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* NASM: relicense under the 2-clause BSD licenseH. Peter Anvin2009-07-061-12/+0
| | | | | | | | *To the best of my knowledge*, we now have authorization from everyone who has significantly contributed to NASM in the past. As such, change the license to the 2-clause BSD license. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Add copyright headers to the *.c/*.h files in the main directoryH. Peter Anvin2009-06-281-6/+45
| | | | | | | | | | Add copyright headers to the *.c/*.h files in the main directory. For files where I'm sure enough that we have all the approvals, I have given them the 2-BSD license, the others have been given the "LGPL for now" license header. Most of them can probably be changed after auditing. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* ndisasm: fix disassembly of JRCXZH. Peter Anvin2009-06-261-1/+1
| | | | | | | Fix the disassembly of JRCXZ; in 64-bit mode, we should only accept JECXZ for disassembly with 32-bit address size override. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Add support for instructions which always use low 8-bit registersH. Peter Anvin2009-06-241-2/+6
| | | | | | | | | Add a byte code to explicitly support instructions which only uses the low 8-bit registers (as if a REX prefix always was present.) This is usable for instructions which are officially documented as using "the low byte of a 32-bit register" and so on. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Add symbolic constants for REX_V "classes" (VEX, XOP, ...)H. Peter Anvin2009-05-081-4/+4
| | | | Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Use lower case for VEX and XOP in instructions tableH. Peter Anvin2009-05-031-2/+2
| | | | | | | | Use lower case for VEX and XOP ("vex", "xop") to avoid visual confusion (and in the future potential real confusion) with upper-case hexadecimal numbers. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Infrastructure support for AMD's new XOP prefixH. Peter Anvin2009-05-031-1/+24
| | | | | | | Handle AMD's XOP prefixes; they use basically the same encoding as VEX prefixes, so treat them simply as a variant of VEX. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* disasm: fix reversed REP vs REPNE in eatbyte()H. Peter Anvin2009-03-191-2/+2
| | | | F2 is REPNE, F3 is REP(E)
* disasm: when no instruction is found, consider a naked prefixH. Peter Anvin2009-03-181-2/+80
| | | | | If we can't find a matching instruction, rather than printing it as a "db" literal, consider first if we can disassemble it as a naked prefix.
* BR 2592476: Treat WAIT as a prefix even though it's really an instructionH. Peter Anvin2009-02-211-35/+20
| | | | | | WAIT is technically an instruction, but from an assembler standpoint it behaves as if it had been a prefix. In particular, it has to be ordered *before* any real hardware prefixes.
* disasm: introduce opyH. Peter Anvin2008-10-251-3/+4
| | | | | | | Introduce the opy pointer into the disassembler, and use it where appropriate. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* disasm: extension byte support in the disassemblerH. Peter Anvin2008-10-231-12/+20
| | | | | | | Add support to the disassembler for the extension bytes (for operand 4+). Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Add extension bytecodes to support operands 4+H. Peter Anvin2008-10-231-0/+1
| | | | | | | | | | The bytecode format assumes max 4 operands pretty strictly, but we already have one instruction with 5 operands, and it's likely to get more. Support them via extension prefixes (similar to REX prefixes). For bytecodes which use argument bytes we encode the number directly, however. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* disasm: collapse all the segment register push/pop bytecodesH. Peter Anvin2008-10-091-59/+2
| | | | | | | | As far as the disassembler is concerned, the segment register push/pop bytecodes can be collapsed to a simple expression; the remaining differences are handled by the filter expressions in insns.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Reshuffle and move the bytecodes for segment register push/popH. Peter Anvin2008-10-081-61/+61
| | | | | | | | | Reshuffle the bytecodes for segment register push/pop to make more sense, and move them from \4 to \344, thus freeing up the single-digit bytecodes \4..\7 for future use. It doesn't really make sense to use single-digit bytecodes for this very oddball use. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* New opcode for 32->64 bit sign-extended immediate with warningH. Peter Anvin2008-10-071-0/+1
| | | | | | | | | | | | Add a new opcode for 32->64 bit sign-extended immediate, with warning on the number not matching. This unfortunately calls for an audit of all the \4[0123] opcodes, if they should be replaced by \25[4567]. This only replaces one instruction (MOV reg64,imm32); other instructions need to be considered. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* New opcodes to deal with 8-bit immediate sign extended to opsizeH. Peter Anvin2008-10-061-0/+1
| | | | | | | | | New opcodes to deal with 8-bit immediates which are then sign-extended to the operand size. These allow us to warn appropriately. Not sure I'm using these in all the proper places; need audit of all uses of the \14..\17 opcodes. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* BR 2029829: Accept VIA XCRYPT instructions with or without REPH. Peter Anvin2008-08-281-0/+4
| | | | | | | Accept the VIA XCRYPT instructions either with or without a REP prefix, as documented. Add the missing XCRYPTCTR instruction.
* BR 2062342: ndisasm: r12 *can* be an index registerH. Peter Anvin2008-08-201-2/+2
| | | | | | | R12 can be used as an index register. Special encodings in the modr/m byte are done *without* consideration for the REX prefix, but special encodings in the SIB byte *do* take the REX prefix into consideration, since it doesn't affect the overall instruction format.
* BR 2028910: fix decoding of VEX prefixes in 16- and 32-bit modeH. Peter Anvin2008-07-301-16/+17
| | | | | | We would incorrectly set a bunch of VEX-related state for C4 and C5 bytes, even though we had already rejected it as not a VEX prefix due to the top two bits of the following byte not being 11.
* ndisasm: the high bit of is4 bytes is ignored in 32-bit modeH. Peter Anvin2008-05-261-3/+4
| | | | | Mask the high bit of is4 bytes in 32-bit mode. Provide a generic "regmask" variable that we can use for equivalent purposes as needed.
* Add tokens vex.ww and vex.wx; vex.wx is the defaultH. Peter Anvin2008-05-221-2/+6
| | | | | | Add vex.ww (for VEX.W follows REX.W) and vex.wx (for VEX.W is a don't care); vex.wx is the default since that seems to match existing usage better.
* insnsn.c: cleaner to *not* separate out conditional instructionsH. Peter Anvin2008-05-211-5/+4
| | | | | | | The disassembler code gets cleaner if we do *not* separate out the conditional instructions; instead, rely on the fact that the conditionals are always at the end and use FIRST_COND_OPCODE as a barrier.
* Disassembler: select table based on VEX prefixesH. Peter Anvin2008-05-211-1/+14
| | | | | | | | | | We can use the new VEX prefixes to select into a large table of new opcode spaces. Since the table is (currently) sparse, add logic so we don't end up producing tons of empty tables for no good reason. This is also necessary since VEX is likely to reuse opcode bytes that would appear as prefixes at some point, which would cause conflicts with the regular tables.
* Fix display for fixed xmm0/ymm0, SSE redundant prefixesH. Peter Anvin2008-05-211-0/+7
| | | | | | | | All singleton registers need to be displayable from register flags alone! When using the new 0360..0363 codes, make sure we appropriate avoid displaying the legacy use of the prefixes.
* VEX prefixes apply to VEX instructions only...H. Peter Anvin2008-05-201-0/+6
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* Handle is4 bytes without meaningful information in the bottom bitsH. Peter Anvin2008-05-201-0/+10
| | | | | | Support is4 bytes without meaningful information in the bottom bits. This is equivalent to /is4=0 for the assembler, but makes the bottom bits don't care for the disassembler.
* ndisasm: simple compare for conditional opcodes, no loopH. Peter Anvin2008-05-201-12/+9
| | | | | | We had a completely unnecessary loop to test for conditional opcodes. Since we always put the conditional opcodes at the end, we might as well just remember where that list starts and compare against it.
* Avoid #including .c files; instead compile as separate unitsH. Peter Anvin2008-05-201-46/+40
| | | | | | Don't #include .c files, even if they are auto-generated; instead compile them as separate compilation units and let the linker do its job.
* Add DY, YWORD, and the SY instruction flagH. Peter Anvin2008-05-201-0/+3
| | | | | Add the DY instruction, YWORD keyword, and an SY marker for instruction sizes. Add a few more AVX sample instructions.
* Same some space by introducing shorthand byte codes for SSE prefixesH. Peter Anvin2008-05-201-0/+20
| | | | | | | Properly done, all SSE instructions which has the 66/F2/F3 opcode multiplex need two prefixes: one to control the use of OSP and one to control the use of REP. However, it's a four-way select: np/66/F2/F3; so introduce shorthand bytecodes for that purpose.
* Remove special hacks to avoid zero bytecodesH. Peter Anvin2008-05-121-5/+0
| | | | | We can now have zero bytecodes with impunity, so remove any special hacks we had to avoid zeroes in the bytecode.
* Add support for register-number immediates with fixed 4-bit valuesH. Peter Anvin2008-05-061-0/+13
| | | | | Add support for imm8 bytes which has a register value in the top four bits and an arbitrary fixed value in the bottom four bits.
* Initial NDISASM support for AVX instructions/VEX prefixesH. Peter Anvin2008-05-051-9/+121
| | | | | | | Initial NDISASM support for AVX instructions and VEX prefixes. It doesn't mean it's correct, but it seems to match my current understanding. It can disassemble *some*, but not *all*, of the AVX test cases (which are known to be at least partially incorrect...)
* First cut at AVX machinery.H. Peter Anvin2008-05-041-0/+10
| | | | | | | | | First cut at AVX machinery support. The only instruction implemented is VPERMIL2PS, and it's probably buggy. I'm checking this in with the hope that other people can start helping out with (a) testing this, and (b) adding instructions. NDISASM support is not there yet.
* disasm: relative operands are signed, not unsignedH. Peter Anvin2008-01-021-4/+7
| | | | | Relative operands are signed, not unsigned; record them as such and then apply proper truncation after offset addition.
* regularized spelling of license to match name of LICENSE fileBeroset2007-12-291-1/+1
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* disasm: 32-bit index registers were displayed as 64 bitsH. Peter Anvin2007-12-261-1/+1
| | | | | | | | | Fix bug where 32-bit index registers got incorrectly displayed as 64 bits: 00000000 678B040B mov eax,[ebx+rcx] 00000004 678B044B mov eax,[ebx+rcx*2] 00000008 678B045B mov eax,[ebx+rbx*2]
* BR 1834292: Fix multiple disassembler bugsH. Peter Anvin2007-11-181-4/+23
| | | | | | | | | | | | - Correct the building on the disassembler decision tree. - Handle SSE instructions with F2 prefix (\332) correctly. - Mark instructions which are now used as prefixes with ND. (In a future version when we have better CPU version handling, we should probably build the decision tree at runtime based on the selected CPU feature sets.) - Sanitize the handling of \144-147 and \154-157 in both the assembler and disassembler. They take an opcode byte as argument; don't pretend they don't.
* Address data is int64_t; simplify writing an address objectH. Peter Anvin2007-11-131-1/+1
| | | | | | | Address data is always int64_t even if the size itself is smaller; this was broken on bigendian hosts (still need testing!) Create simple "write sized object" macros.
* ndisasm: factor out the common operand-extraction codeH. Peter Anvin2007-11-121-38/+41
| | | | | Factor out the common operand-extraction code in the disassembler, as previously done in the assembler.
* Un-special-case "xchg rax,rax"; disassemble o64H. Peter Anvin2007-11-121-5/+30
| | | | | | | | | | | | Un-special-case "xchg rax,rax"; allow it to be encoded as 48 90 for orthogonality's sake. It's a no-op, to be sure, but so are many other instructions. "xchg eax,eax" is still special-cased in 64-bit mode since it is not a no-op; unadorned opcode 90 is now simply "nop" and nothing else. Make the disassembler detect unused REX.W and display them as an "o64" prefix.
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