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* assemble: Only treat a displacement as signed if it is < asizesignrelH. Peter Anvin2013-11-262-17/+22
| | | | | | | | | | | | Only generate a signed relocation if the displacement size is less than the address size. This matters when involving address size overrides. It is technically impossible to do this one perfectly, because it is never really knowable if the displacement offset is used as a base or an index. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* test: Add a test for various 32- and 64-bit relocationsH. Peter Anvin2013-11-261-0/+13
| | | | | | Test signedness in a couple of different contexts. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* assemble: Emit signed relocations where appropriateH. Peter Anvin2013-11-261-8/+11
| | | | | | | | Emit signed relocations where we know they are necessary. This is not at all exhaustive; in particular we are missing this for a number of 8- and 16-bit cases, and probably others. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* listing: handle negative (signed) address size valuesH. Peter Anvin2013-11-261-1/+1
| | | | | | The listing module also needs to know about this new convention. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* output: Allow OUT_ADDRESS with a negative size to mean signed relocationH. Peter Anvin2013-11-2613-86/+154
| | | | | | This only matters for ELF64/ELFx32, at least for now. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: In iflag_cmp() scan from the most significant word downH. Peter Anvin2013-11-262-4/+7
| | | | | | | | | | | In order for iflag_cmp() to return an ordering that makes sense, we need to scan from the most significant word downward. That way the bits with the higher index consistently are the more significant. This fixes the disassembler vendor selection algorithm. While we are doing that, make that dependency more explicit in the comments. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: Drop the use of double underscoresH. Peter Anvin2013-11-241-9/+9
| | | | | | | | Double underscores are reserved for the implementation, i.e. the C compiler and its libraries. NASM is an application and should not use this namespace. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: Make the insns_flags array constH. Peter Anvin2013-11-242-9/+11
| | | | | | | Make the insns_flags array const, and change the helper functions to match. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns.dat: Fix a typo in a commentH. Peter Anvin2013-11-241-1/+1
| | | | | | isnsn-iflags.pl not insns-iflag.pl. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: Move instruction flag commentH. Peter Anvin2013-11-243-35/+29
| | | | | | | Move the instruction flag comment to the Perl file where they are defined. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: remove C99 constructs, don't hardcode the number of wordsH. Peter Anvin2013-11-242-30/+27
| | | | | | | Avoid using C99 constructs when not necessary. Don't hardcode the number of words when we can autodiscover them. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* "make alldeps"H. Peter Anvin2013-11-245-133/+145
| | | | Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* iflag: Fix dependencies, factor out static components of iflag.hH. Peter Anvin2013-11-245-216/+223
| | | | | | | | | | Multi-dependencies don't work as expected, especially not across Make versions, this is why we don't use them and read the instructions list multiple times. iflag.h has a lot of static content, so factor out the static content. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* "make alldeps"H. Peter Anvin2013-11-245-30/+48
| | | | Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* insns: Restore back MMX,FPU flagsCyrill Gorcunov2013-11-242-38/+23
| | | | | | | | | | | In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Update .gitignoreCyrill Gorcunov2013-11-241-0/+2
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* make: Update depsCyrill Gorcunov2013-11-245-126/+146
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* iflag: Start using new instruction flags engineCyrill Gorcunov2013-11-2413-234/+182
| | | | | | Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Introduce insns-flags.plCyrill Gorcunov2013-11-241-0/+410
| | | | | | | | | | | | | | | | | | | | | | | | It been found that 64 bits for instruction flags is too small, so instead we start using indirect addressing scheme to keep instruction flags in bitvectors instead. Using one bitvector per instruction template entry is wastefull (especially if vector grow in future, at moment it's 128 bit length), so we use indirect addressing, which is generated as follow - read instruction flags from insns.dat - flag sequence sorted and joined into one key string - this key string become a hash index - all hash entries are compacted into one array - every instruction template uses array offset instead of flags bitfield Just for info, at moment we have 195 unique flags combination, but since instruction template will use index as unsigned integer, we can use a way more wider combination of flags in future. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* make: Add 'golden' targetCyrill Gorcunov2013-11-241-0/+3
| | | | | | | | We've 'test' target in toplevel Makefile, lets be complete and allow to generate "golden" tests from toplevel as well. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* bnd: Drop bnd prefix for relaxed short jmp instructionsJin Kyu Song2013-11-224-97/+65
| | | | | | | | | | | | Reverted the redundant branch instruction patterns for bnd prefix. And when a relaxed jmp instruction becomes a short (Jb) form, bnd prefix is not needed because it does not initialize bnd registers. So in that case, bnd prefix is silently dropped. BND JMP foo -> drops bnd prefix BND JMP short foo -> shows an explicit error Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disp8: Consolidate a logic to get compressed displacementJin Kyu Song2013-11-205-155/+181
| | | | | | | | | Consolidated two separate but similar functions in nasm and ndisasm into a commonly linked source code. To encode and decode the compressed displacement (disp8*N) for EVEX, N value should be derived using various conditions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: Add suport for bnd registersJin Kyu Song2013-11-201-0/+7
| | | | | | MPX uses a new bnd registers and a new mib syntax. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: Add EVEX decorator syntaxJin Kyu Song2013-11-201-9/+92
| | | | | | | Broadcasting, opmask, embedded rounding and SAE decorators are not added at proper position. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: Add ZMM vsibJin Kyu Song2013-11-201-4/+12
| | | | | | | ZMM registers can be used for vsib index and the number of registers has been increased to 32. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: Support EVEX compressed displacementJin Kyu Song2013-11-201-11/+107
| | | | | | | When tuple type is indicated in the bytecode, disp8 is treated as a compressed disp and gets calculated back to disp8*N. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: Add basic AVX512 supportJin Kyu Song2013-11-203-6/+100
| | | | | | | Disassembler can translate EVEX prefix, count up to 32 vector registers and recognize new ZMM / opmask registers. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: style cleanupJin Kyu Song2013-11-201-682/+682
| | | | | | Fix indentation. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* match: Check the number of elements in broadcasting operandsJin Kyu Song2013-11-203-2/+36
| | | | | | | | | | | | | | | The broadcasting decorator {1to##} must describe exactly how many times the memory element is repeated in order to clearly match the correct instruction format. For example, vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* match: Improve broadcast opsize matchingJin Kyu Song2013-11-201-20/+35
| | | | | | | | | | Broadcasting operand size is different from the original operand size because 32b or 64b element is repeated to form a vector. So when matching a broadcasting operand, opsize should be treated differently. The broadcasting element size is specified in the decorator information. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* Build: Suppress warning messagesJin Kyu Song2013-11-202-2/+2
| | | | | | | Giving a correct printf format specifier supresses the warning message. And a local pointer variable is initialized with NULL. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* AVX-512: Add {evex} instruction prefixJin Kyu Song2013-11-204-0/+14
| | | | | | | For instructions that can be encoded either in VEX or EVEX, {evex} forces nasm to encode in EVEX. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* PREFETCHWT1: Add a new instruction flagJin Kyu Song2013-11-202-1/+2
| | | | | | | PREFETCHWT1 instruction's CPUID was TBD before. Now it has its new CPUID bit : PREFETCHWT1 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* AVX512: Update instruction groupJin Kyu Song2013-11-201-2/+2
| | | | | | | CPUID bit for vptestnm[dq] changed. vptestnm[dq]: AVX512CD -> AVX512F Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* MPX: Move BND prefix indication from bytecode to iflagsJin Kyu Song2013-11-205-56/+50
| | | | | | | | As BND prefix validity check conflicts with jcc8 prefix, IF_BND is added for the instruction templates which can have bnd prefix for preserving the content of bound register. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* MPX: Adapt GAS's mib syntax with an index reg onlyJin Kyu Song2013-11-202-4/+16
| | | | | | | | GAS uses *1 multiplier for explicitly marking an index register in mib operand. e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format So only for mib operands, this is encoded same as gas does. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* iflags: Use UINT64_C() for 64bit valuesJin Kyu Song2013-11-201-79/+79
| | | | | | UINT64_C() macro is used for iflags as it becomes 64bit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* SHA: SHA test casesJin Kyu Song2013-11-202-0/+61
| | | | | | 32bit and 64bit test asm files. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* SHA: Add SHA instructionsJin Kyu Song2013-11-202-0/+10
| | | | | | New instruction extensions of SHA family are added. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* MPX: Add test cases for MPXJin Kyu Song2013-11-202-0/+202
| | | | | | | MPX test asm files are added. These include all three different styles of mib syntax (NASM, ICC and gas). Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* MPX: Add BND prefix for branch instructionsJin Kyu Song2013-11-208-3/+75
| | | | | | | BND prefix is used for adding bounds checking protection across flow control changes such as call, ret, jmp and jcc calls. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* MPX: Add MPX instructionsJin Kyu Song2013-11-207-2/+61
| | | | | | | | | | | | | Added MPX instructions and corresponding parser and encoder. ICC style mib - base + disp and index are separate - is supported. E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index As a supplement to NASM style mib - split EA - parser, omitted base+disp is now treated as 0 displacement. E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* disasm: add support for emitting split EA formatH. Peter Anvin2013-11-202-2/+16
| | | | | | | | Add support for emitting split EA format in the disassembler, indicated by the MIB instruction flag. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* parser: support split base,index effective addressH. Peter Anvin2013-11-202-18/+90
| | | | | | | Mostly intended for the "mib" expressions in BNDLDX/BNDSTX. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* parse: factor out mref parsingH. Peter Anvin2013-11-201-125/+132
| | | | | | | | | Factor out the parsing of an mref from parse_line(). In order to support the [base,index] syntax we need to be able to parse an mref in two steps. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* parser: simplify code by keeping a pointer to the current operandH. Peter Anvin2013-11-201-152/+132
| | | | | | | | There is an awful lot of syntax-heavy "result->oprs[operand]" going on; simplify by making a pointer to the current operand. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* AVX-512: Add perfomtest-compliant headers to test casesJin Kyu Song2013-11-204-1/+5
| | | | | | | test/avx512*.asm files are now tested by using perfomtest.pl Refer to pefomtest help message for the usage. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* BR3392270: preproc: Handle all token chains in mmacro params rangeCyrill Gorcunov2013-11-091-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | A typical example is | | %macro m0 0-* | %rep %0 | m0 arg is %1 | %rotate 1 | %endrep | %endmacro | | %macro m1 0-* | m0 %{1:-1} | %endmacro | | m1 a=b, c=d If passed with nasm -E the output must be like m0 arg is a=b m0 arg is c=d http://bugzilla.nasm.us/show_bug.cgi?id=3392270 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Add (redundant) parentheses around bit tests mixed with &&H. Peter Anvin2013-11-081-3/+3
| | | | | | | It is easy to get confused when mixing & and &&, so add redundant parenteses for clarity. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* REX: Set REX bits in accordance with 32-register environmentJin Kyu Song2013-11-081-7/+7
| | | | | | | | | | REX.RXB bits were set for high-8 registers previously. Since high-16 zmm registers are newly added, those bits should be set as one bit of binary number of register value. Similarly EVEX.R'/V'/X should be set in the same manner. Authored-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
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