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* insns: Restore back MMX,FPU flagsinsns-flagsCyrill Gorcunov2013-11-102-38/+23
| | | | | | | | | | | In commit 9bb987d8e0330429afba42015b1fc7c7ca0d1b16 we had to drop some flags due to flags type used in nasm code. Since now flags internal structure is reworked, we can restore them back. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Update .gitignoreCyrill Gorcunov2013-11-101-0/+2
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* make: Update depsCyrill Gorcunov2013-11-105-126/+146
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* iflag: Start using new instruction flags engineCyrill Gorcunov2013-11-1013-216/+173
| | | | | | Here we start using instruction flags generator. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Introduce insns-flags.plCyrill Gorcunov2013-11-101-0/+405
| | | | | | | | | | | | | | | | | | | | | | | | It been found that 64 bits for instruction flags is too small, so instead we start using indirect addressing scheme to keep instruction flags in bitvectors instead. Using one bitvector per instruction template entry is wastefull (especially if vector grow in future, at moment it's 128 bit length), so we use indirect addressing, which is generated as follow - read instruction flags from insns.dat - flag sequence sorted and joined into one key string - this key string become a hash index - all hash entries are compacted into one array - every instruction template uses array offset instead of flags bitfield Just for info, at moment we have 195 unique flags combination, but since instruction template will use index as unsigned integer, we can use a way more wider combination of flags in future. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* BR3392270: preproc: Handle all token chains in mmacro params rangeCyrill Gorcunov2013-11-091-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | A typical example is | | %macro m0 0-* | %rep %0 | m0 arg is %1 | %rotate 1 | %endrep | %endmacro | | %macro m1 0-* | m0 %{1:-1} | %endmacro | | m1 a=b, c=d If passed with nasm -E the output must be like m0 arg is a=b m0 arg is c=d http://bugzilla.nasm.us/show_bug.cgi?id=3392270 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Add (redundant) parentheses around bit tests mixed with &&H. Peter Anvin2013-11-081-3/+3
| | | | | | | It is easy to get confused when mixing & and &&, so add redundant parenteses for clarity. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* REX: Set REX bits in accordance with 32-register environmentJin Kyu Song2013-11-081-7/+7
| | | | | | | | | | REX.RXB bits were set for high-8 registers previously. Since high-16 zmm registers are newly added, those bits should be set as one bit of binary number of register value. Similarly EVEX.R'/V'/X should be set in the same manner. Authored-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* Revert "make: Remove generated files on clean target"Cyrill Gorcunov2013-10-281-4/+1
| | | | | | | | | This reverts commit b6c7291b3d1f904b20955c3f9829b8cc92801227. We already have this cleanup stage in "cleaner" target, I managed to miss it. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* make: Remove generated files on clean targetCyrill Gorcunov2013-10-271-1/+4
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Merge remote-tracking branch 'origin/master'H. Peter Anvin2013-10-245-195/+212
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| * Run "make alldeps" to update dependenciesH. Peter Anvin2013-10-245-195/+212
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* | Makefile.in: always run "make alldeps" when "make dist"H. Peter Anvin2013-10-241-1/+3
|/ | | | | | | "make dist" (tarball generation) really should include "make alldeps" so the Makefile dependencies are correct. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Makefile.in: generate manpages for "make dist"H. Peter Anvin2013-10-241-2/+6
| | | | | | Make sure the "dist" target generates the man pages. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* Revert "build: Include pregenerated nasm manpages"H. Peter Anvin2013-10-244-543/+15
| | | | | | | | | | This reverts commit 99427bdb6c85c812665f6d7b36ac520a631c5b23. We don't include generated files in the repository, instead we should pregenerate them for the tarball generation, just as we do for the Perl-generated files. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* macros.pl: Remove superfluous whitespaceH. Peter Anvin2013-10-191-0/+22
| | | | | | | Squeeze multiple whitespace characters together, since they have no semantic function. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* iflags: Eliminate perl smart match operatorJin Kyu Song2013-10-071-1/+1
| | | | | | | | | As smart match operator reuiqres perl version 5.10.1 or later, it is replaced with grep function. This part of code is going to be completely removed once iflags renovataion is done. This commit is a quick fix for a build error. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
* Merge branch 'nasm-2.10.xx'Cyrill Gorcunov2013-10-031-3/+36
|\ | | | | | | | | * nasm-2.10.xx: coff: Better handling of section redefinition
| * coff: Better handling of section redefinitionnasm-2.10.xxMarat Dukhan2013-10-031-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if we try to define an already defined section and specify section flags, NASM will output "warning: section attributes ignored on redeclaration of section %SECTIONNAME%". The patch modifies this behaviour: 1. If the previous section definition differs only in alignment flags, no warning is generated 2. If the new definition implies larger alignment, it overrides the previous section alignment 3. If the new definition specifies any section alignment, the content of the section will be aligned on the new boundary (i.e. the effect is the same as if there was ALIGN macro) Signed-off-by: Marat Dukhan <maratek@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* | Add support for DZ and RESZ, document the ZWORD keywordH. Peter Anvin2013-10-024-29/+40
| | | | | | | | | | | | | | Add the DZ and RESZ pseudoinstructions and add ZWORD to the documentation. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* | NASM 2.11rc1nasm-2.11rc1H. Peter Anvin2013-10-021-1/+1
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* | NASM 2.10rc1H. Peter Anvin2013-10-021-1/+1
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* | Merge branch 'avx512'H. Peter Anvin2013-10-0225-161/+9088
|\ \ | |/ |/| | | | | | | | | | | AVX512 is ready enough that it will realistically be in version 2.11. Add AVX512 to the master branch; for legacy branch maintenance use the nasm-2.10.xx branch. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
| * AVX-512: Fix bugs related to uninitialized variablesavx512Jin Kyu Song2013-09-211-1/+3
| | | | | | | | | | | | | | | | | | | | Initialized disp8 to avoid a case that disp8 encoded instead of the actual offset value. Added a checking routine for basereg value before using it as an index of array. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Added AVX-512PF instructionsJin Kyu Song2013-09-143-0/+106
| | | | | | | | | | | | | | | | | | | | | | Added Prefetch (AVX-512PF) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1. CPUID feature flag for PREFETCHWT1 is TBD but PREFETCHWT1 is included in this commit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add AVX-512ER instructionsJin Kyu Song2013-09-144-3/+158
| | | | | | | | | | | | | | | | | | | | Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add AVX-512CD instructionsJin Kyu Song2013-09-143-0/+116
| | | | | | | | | | | | | | | | | | Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add Pseudo-ops for CMP instructionsJin Kyu Song2013-09-073-5/+2531
| | | | | | | | | | | | | | | | Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on. Test case is also updated to validate them. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Reorder instructions in insns.datJin Kyu Song2013-09-071-57/+57
| | | | | | | | | | | | | | | | | | | | | | Within a same instruction mnemonic, instructions are reordered in order of opcode byte value. Therefore when there are two possible opcode candidates, smaller opcode is picked now. e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix rounding mode value in EVEX prefix with SAEJin Kyu Song2013-09-072-7/+11
| | | | | | | | | | | | | | | | If SAE is set, VL(vector length) is implied to be 512. EVEX.L'L (=EVEX.RC) is set to 00b by default. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add test case for opmask instructionsJin Kyu Song2013-08-292-4578/+24
| | | | | | | | | | | | | | | | | | | | Added K* instructions test cases in test/avx512f.asm. The previous test case from GNU AS were repeating the same instruction twice, so the repeated half part is removed. Changed the python script (gas2nasm.py) to include opmask instructions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Remove trailing space and align columnsJin Kyu Song2013-08-292-2/+2
| | | | | | | | | | | | | | Cosmetic change Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add OPMASK instructionsJin Kyu Song2013-08-292-15/+33
| | | | | | | | | | | | | | | | | | Added opmask instructions (kandw and etc). Defined KREG and RM_K aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat look neat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add IF_SPMASK and fix IF_PFMASKJin Kyu Song2013-08-291-1/+2
| | | | | | | | | | | | | | | | Defined IF_SPMASK for specific processor types and fixed IF_PFMASK to mask the exact preferred bits only. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix bug in checking high-16 registersJin Kyu Song2013-08-291-1/+1
| | | | | | | | | | | | | | Register value needs to be checked. Previous patch compared with reg_enum. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix commentsJin Kyu Song2013-08-293-3/+3
| | | | | | | | | | | | | | Fixed or purged some old comments and added a comment for a previous patch. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Remember the position of operand with broadcast or embedded roundingJin Kyu Song2013-08-293-16/+15
| | | | | | | | | | | | | | | | | | | | | | It was not so straight forward to find the postion of operand that has a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions) decorator out from operands types or bytecode. Remebering the postion of the operand of interest in the parser reduces the burden that assembler looks through the operands. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add a feature to generate a raw bytecode fileJin Kyu Song2013-08-281-0/+11
| | | | | | | | | | | | | | | | From gas testsuite file, a text file containing raw bytecodes is useful when verifying the output of NASM. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add a test case for EVEX encoded instructionsJin Kyu Song2013-08-282-0/+9271
| | | | | | | | | | | | | | | | | | This was converted from a gas testsuite. (gas/testsuite/gas/i386/x86-64-avx512f-intel.d) A python script that is used for converting is also included. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix match function to check the range of registersJin Kyu Song2013-08-281-0/+8
| | | | | | | | | | | | | | | | | | High-16 registers of XMM and YMM need to be encoded with EVEX not VEX. Even if all the operand types match with VEX instruction format, it should use EVEX instead. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Change the data type for instruction flagsJin Kyu Song2013-08-2810-61/+81
| | | | | | | | | | | | | | | | | | | | | | | | Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix a bug in calculating Disp8*N valueJin Kyu Song2013-08-281-1/+1
| | | | | | | | | | | | | | | | Fixed a bug that derived an incorrect N value for tuple types of T2, T4, T8. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Find the correct position of the last SIMD opJin Kyu Song2013-08-281-0/+2
| | | | | | | | | | | | | | | | Since embedded rounding mode is following the last SIMD op, GPR op should be skipped when finding the last SIMD op. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Moved {er} decorator position next to the last SIMD opJin Kyu Song2013-08-281-8/+9
| | | | | | | | | | | | | | | | | | | | | | This is for following the current syntax used in gas even though this is not SDM conforming. According to SDM, {er} should follow the last GPR op not SIMD op. e.g. SDM : VCVTSI2SD xmm1, xmm2, r/m64{er} NASM : VCVTSI2SD xmm1, xmm2{er}, r/m64 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix parser to handle opmask decorator correctlyJin Kyu Song2013-08-221-5/+8
| | | | | | | | | | | | | | | | When a memory reference operand is a destination, this could have an opmask decorator as well. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add ZWORD keywordJin Kyu Song2013-08-225-0/+12
| | | | | | | | | | | | | | ZWORD (512 bits) keyword is added Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Fix instruction match functionJin Kyu Song2013-08-223-7/+48
| | | | | | | | | | | | | | | | | | | | When an instruction allows broadcasting, the memory element size is different from the size of normal memory operation. This information is provided in a decoflags field, so it should try to match those properties before it fails. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Reword comment about opmask decoratorsJin Kyu Song2013-08-221-1/+1
| | | | | | | | | | | | | | Previous comment was not so clear. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Handle curly braces in multi-line macro parametersJin Kyu Song2013-08-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Multi-line macro uses curly braces for enclosing a parameter containing comma(s). Passing curly braces as a part of a parameter which is already enclosed with braces confuses the macro expander. Escape character '\' is prefixed in this case. e.g.) mmacro {1,2,3}, {4,\{5,6\}} mmacro gets 2 parameters of '1,2,3' and '4,{5,6}' Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| * AVX-512: Add EVEX encoding and new instructionsJin Kyu Song2013-08-169-75/+925
| | | | | | | | | | | | | | | | | | EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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