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* AVX-512: Fix bugs related to uninitialized variablesavx512Jin Kyu Song2013-09-211-1/+3
| | | | | | | | | | Initialized disp8 to avoid a case that disp8 encoded instead of the actual offset value. Added a checking routine for basereg value before using it as an index of array. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Added AVX-512PF instructionsJin Kyu Song2013-09-143-0/+106
| | | | | | | | | | | Added Prefetch (AVX-512PF) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1. CPUID feature flag for PREFETCHWT1 is TBD but PREFETCHWT1 is included in this commit. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add AVX-512ER instructionsJin Kyu Song2013-09-144-3/+158
| | | | | | | | | | Added Exponential and Reciprocal (AVX-512ER) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1. IF_AVX512 is now shared by all AVX-512* instructions as a bit mask. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add AVX-512CD instructionsJin Kyu Song2013-09-143-0/+116
| | | | | | | | | Added Conflict Detection (AVX-512CD) instructions. These instructions are supported if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add Pseudo-ops for CMP instructionsJin Kyu Song2013-09-073-5/+2531
| | | | | | | | Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on. Test case is also updated to validate them. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Reorder instructions in insns.datJin Kyu Song2013-09-071-57/+57
| | | | | | | | | | | Within a same instruction mnemonic, instructions are reordered in order of opcode byte value. Therefore when there are two possible opcode candidates, smaller opcode is picked now. e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix rounding mode value in EVEX prefix with SAEJin Kyu Song2013-09-072-7/+11
| | | | | | | | If SAE is set, VL(vector length) is implied to be 512. EVEX.L'L (=EVEX.RC) is set to 00b by default. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add test case for opmask instructionsJin Kyu Song2013-08-292-4578/+24
| | | | | | | | | | Added K* instructions test cases in test/avx512f.asm. The previous test case from GNU AS were repeating the same instruction twice, so the repeated half part is removed. Changed the python script (gas2nasm.py) to include opmask instructions. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Remove trailing space and align columnsJin Kyu Song2013-08-292-2/+2
| | | | | | | Cosmetic change Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add OPMASK instructionsJin Kyu Song2013-08-292-15/+33
| | | | | | | | | Added opmask instructions (kandw and etc). Defined KREG and RM_K aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat look neat. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add IF_SPMASK and fix IF_PFMASKJin Kyu Song2013-08-291-1/+2
| | | | | | | | Defined IF_SPMASK for specific processor types and fixed IF_PFMASK to mask the exact preferred bits only. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix bug in checking high-16 registersJin Kyu Song2013-08-291-1/+1
| | | | | | | Register value needs to be checked. Previous patch compared with reg_enum. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix commentsJin Kyu Song2013-08-293-3/+3
| | | | | | | Fixed or purged some old comments and added a comment for a previous patch. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Remember the position of operand with broadcast or embedded roundingJin Kyu Song2013-08-293-16/+15
| | | | | | | | | | | It was not so straight forward to find the postion of operand that has a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions) decorator out from operands types or bytecode. Remebering the postion of the operand of interest in the parser reduces the burden that assembler looks through the operands. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add a feature to generate a raw bytecode fileJin Kyu Song2013-08-281-0/+11
| | | | | | | | From gas testsuite file, a text file containing raw bytecodes is useful when verifying the output of NASM. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add a test case for EVEX encoded instructionsJin Kyu Song2013-08-282-0/+9271
| | | | | | | | | This was converted from a gas testsuite. (gas/testsuite/gas/i386/x86-64-avx512f-intel.d) A python script that is used for converting is also included. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix match function to check the range of registersJin Kyu Song2013-08-281-0/+8
| | | | | | | | | High-16 registers of XMM and YMM need to be encoded with EVEX not VEX. Even if all the operand types match with VEX instruction format, it should use EVEX instead. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Change the data type for instruction flagsJin Kyu Song2013-08-2810-61/+81
| | | | | | | | | | | | Increased the size of data type for instruction flags from 32bits to 64bits. And a new type (iflags_t) is defined for better maintainability. Bigger data type is needed because more instruction set types are coming but there were not enough space for them. Since they are not bit masks, only one instruction set is allowed for each instruction. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix a bug in calculating Disp8*N valueJin Kyu Song2013-08-281-1/+1
| | | | | | | | Fixed a bug that derived an incorrect N value for tuple types of T2, T4, T8. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Find the correct position of the last SIMD opJin Kyu Song2013-08-281-0/+2
| | | | | | | | Since embedded rounding mode is following the last SIMD op, GPR op should be skipped when finding the last SIMD op. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Moved {er} decorator position next to the last SIMD opJin Kyu Song2013-08-281-8/+9
| | | | | | | | | | | This is for following the current syntax used in gas even though this is not SDM conforming. According to SDM, {er} should follow the last GPR op not SIMD op. e.g. SDM : VCVTSI2SD xmm1, xmm2, r/m64{er} NASM : VCVTSI2SD xmm1, xmm2{er}, r/m64 Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix parser to handle opmask decorator correctlyJin Kyu Song2013-08-221-5/+8
| | | | | | | | When a memory reference operand is a destination, this could have an opmask decorator as well. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add ZWORD keywordJin Kyu Song2013-08-225-0/+12
| | | | | | | ZWORD (512 bits) keyword is added Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Fix instruction match functionJin Kyu Song2013-08-223-7/+48
| | | | | | | | | | When an instruction allows broadcasting, the memory element size is different from the size of normal memory operation. This information is provided in a decoflags field, so it should try to match those properties before it fails. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Reword comment about opmask decoratorsJin Kyu Song2013-08-221-1/+1
| | | | | | | Previous comment was not so clear. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Handle curly braces in multi-line macro parametersJin Kyu Song2013-08-221-0/+5
| | | | | | | | | | | | | Multi-line macro uses curly braces for enclosing a parameter containing comma(s). Passing curly braces as a part of a parameter which is already enclosed with braces confuses the macro expander. Escape character '\' is prefixed in this case. e.g.) mmacro {1,2,3}, {4,\{5,6\}} mmacro gets 2 parameters of '1,2,3' and '4,{5,6}' Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add EVEX encoding and new instructionsJin Kyu Song2013-08-169-75/+925
| | | | | | | | | EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM), opmask, broadcasting, embedded rounding mode, suppress all exceptions, compressed displacement. Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* AVX-512: Add support for parsing bracesJin Kyu Song2013-08-0610-28/+358
| | | | | | | | | | AVX-512 introduced new syntax using braces for decorators. Opmask, broadcat, rounding control use this new syntax. http://software.intel.com/sites/default/files/319433-015.pdf Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* NASM 2.10.09nasm-2.10.09Cyrill Gorcunov2013-07-231-1/+1
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* doc: changes -- Prepare for 2.10.09Cyrill Gorcunov2013-07-231-0/+4
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* build: Include pregenerated nasm manpagesCyrill Gorcunov2013-07-224-15/+543
| | | | | | | | | | It's been reported that force people to install asciidoc for man pages generation is not acceptible. Just ship them pregenerated. http://bugzilla.nasm.us/show_bug.cgi?id=3392262 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* NASM 2.10.08nasm-2.10.08Cyrill Gorcunov2013-07-211-1/+1
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* doc: changes -- Add fixes for VMOVNTDQA, MOVNTDQA, MOVLPDCyrill Gorcunov2013-07-211-0/+2
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* test: Add br978756Cyrill Gorcunov2013-07-211-0/+7
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* test: Add br3392259Cyrill Gorcunov2013-07-211-0/+8
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix MOVLPDCyrill Gorcunov2013-07-211-2/+2
| | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=978756 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix MOVNTDQA instructionCyrill Gorcunov2013-07-211-1/+1
| | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=3392259 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix VMOVNTDQA instructionCyrill Gorcunov2013-07-211-1/+1
| | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=3392259 Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* changes.src: Prepare for 2.10.08Cyrill Gorcunov2013-07-211-1/+23
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* BR 3392260: Handle instructions only separated by vector SIB sizeH. Peter Anvin2013-07-194-25/+53
| | | | | | | | | | | | | | | | There are two instructions (VGATHERQPS, VPGATHERQD) where the only separation between two forms is the vector length given to the vector SIB. This means the *matcher* has to be able to distinguish instructions by vector SIB length and the matcher only operates on the operands and the instruction flags, not on the bytecode. Export the vector index-ness into the operand flags and add to the matcher. This resolves BR 3392260. Reported-by: Agner <agner@anger.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* parse_line: Shrink code with memset helperCyrill Gorcunov2013-07-161-3/+2
| | | | | | | | We know that P_none = 0 thus instead of using for() statement assign them all in one memset call. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* ea_type: Fix typo in commentCyrill Gorcunov2013-07-141-1/+1
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* autoconf: Warn a user if no asciidoc/xmlto foundCyrill Gorcunov2013-07-051-0/+8
| | | | | | | | | | It's been noticed on nasm forum that we don't complain if no asciidoc/xmlto package installed on a system while they are required for man pages generation. So warn a user then, but still allow to build nasm. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* make: Fix nasm build with MSVCMarat Dukhan2013-06-303-4/+18
| | | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=3392258 Signed-off-by: Marat Dukhan <maratek@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix vspllw instructionMITSUNARI Shigeo2013-06-301-1/+1
| | | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=3392257 Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix vgatherqpd instructionMITSUNARI Shigeo2013-06-011-1/+1
| | | | | Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns: Fix VPMOVSXBQ instructionMITSUNARI Shigeo2013-05-241-1/+1
| | | | | | | http://bugzilla.nasm.us/show_bug.cgi?id=3392254 Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* Make the errors for missing man page tools comprehensibleH. Peter Anvin2013-05-172-7/+9
| | | | | | A lot of confusion was had due to missing asciidoc... Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* test: Add br3392252 testCyrill Gorcunov2013-05-131-0/+43
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
* insns.dat: Add note about AMD TBM instructionsCyrill Gorcunov2013-05-121-1/+1
| | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
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