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| author | H. Peter Anvin <hpa@zytor.com> | 2008-05-04 17:53:31 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-05-04 17:53:31 -0700 |
| commit | d85d250fa229d5ceb73ce5fedfd1087727f53a79 (patch) | |
| tree | 5a51259e0deae99fb8f042c37b467c604cdd27b6 /insns.h | |
| parent | 7117e80702d70ac635e50a05deb85f672bd3a464 (diff) | |
| download | nasm-d85d250fa229d5ceb73ce5fedfd1087727f53a79.tar.gz | |
First cut at AVX machinery.
First cut at AVX machinery support. The only instruction implemented
is VPERMIL2PS, and it's probably buggy. I'm checking this in with the
hope that other people can start helping out with (a) testing this,
and (b) adding instructions.
NDISASM support is not there yet.
Diffstat (limited to 'insns.h')
| -rw-r--r-- | insns.h | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -98,6 +98,7 @@ extern const struct disasm_index itable[256]; #define IF_SSE41 0x00800000UL /* it's an SSE4.1 instruction */ #define IF_SSE42 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_SSE5 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ +#define IF_AVX 0x00800000UL /* HACK NEED TO REORGANIZE THESE BITS */ #define IF_PMASK 0xFF000000UL /* the mask for processor types */ #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */ /* also the highest possible processor */ @@ -114,6 +115,7 @@ extern const struct disasm_index itable[256]; #define IF_PRESCOTT 0x09000000UL /* Prescott instructions */ #define IF_X86_64 0x0A000000UL /* x86-64 instruction (long or legacy mode) */ #define IF_NEHALEM 0x0B000000UL /* Nehalem instruction */ +#define IF_SANDYBANKS 0x0C000000UL /* Sandy Banks instruction */ #define IF_X64 (IF_LONG|IF_X86_64) #define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */ #define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */ |